cardbus_5632.tb

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

	constant skew : time := 4 ns;
	constant HalfCyclePCI : time := 15 ns;
	signal SIM_END : boolean := FALSE;

	-- protocol checker signals
	SIGNAL SERRN_Detected : std_logic;
	SIGNAL PERRN_Detected : std_logic;
	SIGNAL Clear_SERR : std_logic;
	SIGNAL Clear_PERR : std_logic;
	signal Set_Master_Abort : std_logic;
	signal Master_Abort : std_logic;
	signal Clear_Disconnect : std_logic;
	signal Disconnect_Detected : std_logic;
	signal Status : std_logic;

	-- LEDs
	signal led : std_logic_vector(7 downto 0); -- active low LEDs

	--// Programmable On-Board Clock Chip
	signal lclk : std_logic;	   -- on-board clock (20-100 MHz)
	signal s0, s1 : std_logic;	   -- clock speed select

	-- IDT FIFO (uses lclk)
	signal lad : std_logic_vector(31 downto 0); -- 32 bit data (bidirectional)
	signal pae_n, paf_n : std_logic; -- programmable almost empty/full flags (active low)
	signal or_n, ir_n : std_logic; -- empty/full flags (active low)
	signal hf_n : std_logic; -- half full flag (active low)
	signal fwft : std_logic; -- first-word-flow-through
	signal ld : std_logic; -- load for almost empty/full flags
	signal rt : std_logic; -- retransmit
	signal mrs, prs : std_logic; -- master reset, partial reset (unused)
	signal ren, wen : std_logic; -- read enable, write enable (both active low)
	signal oe : std_logic; -- output enable for lad[31:0] (active low)
	signal fs : std_logic; -- frequency select (unused)

	-- Unused 32-bit Expansion Bus (uses lclk and lad)
	signal last :   std_logic;
	signal leot0 :   std_logic;
	signal leot1 :   std_logic;
	signal ldmack0 :   std_logic;
	signal ldmack1 :   std_logic;
	signal ldmareq0 :   std_logic;
	signal ldmareq1 :   std_logic;
	signal lready :   std_logic;
	signal linti :   std_logic;
	signal lads :   std_logic;
	signal lwr :   std_logic;
	signal lreset :   std_logic;
	signal lbe :   std_logic_vector (3 downto 0);

	-- pci_access procedure signals
	signal data_reg : std_logic_vector(63 downto 0);
	signal address_reg : std_logic_vector(63 downto 0);

      -- pci_comp procedure signals
      signal target_bar : std_logic_vector(63 downto 0);

    -- command moniter signals
	signal cmd_mon	:	std_logic_vector(7 downto 0);
	signal test_type	: 	std_logic_vector(7 downto 0);

	-- ctu CardBus IP signals used in test bench to control input signals
	signal tb_BAM, tb_PWM : std_logic;
	signal tb_bvd : std_logic_vector(2 downto 1);
	signal tb_ready, tb_wp, tb_gwake, tb_intr : std_logic;
	signal tb_CBLOCK_n : std_logic;
	signal tb_CAUDIO : std_logic;
	signal tb_CINT_n : std_logic;
	signal tb_clk_resume, tb_clk_stopped : std_logic;
	signal tb_CSTSCHG : std_logic;
	signal tb_locked,  tb_owner_access : std_logic;
	signal tb_CCLKRUN_n : std_logic;
	signal pad_CIS_ADR : std_logic_vector(9 downto 2);
	signal pad_CIS_data : std_logic_vector(31 downto 0);

	-- ct added signals u
	signal tb_clkrun_oe, tb_clkrun_n : std_logic;
	signal passed : integer; -- for counting how many tests passed
	-- ct signals added for testing the CBLOCK -exclusive access part of the cardbus wrapper IP
	signal cblock_test3_go : std_logic;  	-- go flag for test #3
	signal cblock_test3_stop : std_logic;	-- stop flag for test #3
	signal cblock_test4_go : std_logic;		-- go flag for test#4
	signal cblock_test4_stop : std_logic;	-- stop flag for test #4
	signal cblock_test_stop : std_logic;	-- stop signal for all CBLOCK tests
	signal cblock_test3_state : std_logic_vector(2 downto 0);  -- state encoding for test #3
	signal cblock_test4_state : std_logic_vector(2 downto 0);  -- state encoding for test #4

begin --architecture

	-- PCI bus signal pull-ups/downs 
	AD(63 downto 0) <= (others => 'H');
	CBEN(7 downto 0) <= (others => 'H');
	FRAMEN <= 'H';
	IRDYN <= 'H';
	TRDYN <= 'H';
	DEVSELN <= 'H';
	STOPN <= 'H';
	REQ64N <= 'H';
	ACK64N <= 'H';
	PAR <= 'L';
	PAR64 <= 'L';
	PERRN <= 'H';
	SERRN <= 'H';
	INTAN <= 'H';
	intb <= 'H';
	intc <= 'H';
	intd <= 'H';
	sbo <= 'H';
	sdone <= 'H';
	lock <= 'H';
	REQN <= 'H';
	GNTN <= 'H';
	IDSEL <= 'L';
			--add cardbus signals


	-- Local bus signal pull-ups
	lad <= (others => 'H');
	lbe <= (others => 'H');

	-- CardBus pull-up
	tb_CCLKRUN_n <= 'H';


-- instantiate command monitor

cmd_mon_1 : cmd_monitor
	PORT MAP (
				AD => ad,
				CBEN => cben,
				CLK => clk,
		        DEVSELN => devseln,
		        FRAMEN => framen,
				IDSEL => idsel,
				IRDYN => irdyn,
				PAR => par,
		        PERRN => perrn,
		        RSTN => rstn,
		        SERRN => serrn,
		        STOPN => stopn,
		        TRDYN => trdyn,
				test_type => test_type,
				cmd_mon => cmd_mon
	          );

-- instantiate protocol checker

proto_chk_1 : proto_chk
	PORT MAP (CLK => CLK,
	          RSTN => RSTN,
	          FRAMEN => FRAMEN,
	          IRDYN => IRDYN,
	          TRDYN => TRDYN,
	          DEVSELN => DEVSELN,
	          STOPN => STOPN,
	          SERRN => SERRN,
	          PERRN => PERRN,
	          SERRN_Detected => SERRN_Detected,
	          PERRN_Detected => PERRN_Detected,
	          Clear_SERR => Clear_SERR,
	          Clear_PERR => Clear_PERR,
			  Set_Master_Abort => Set_Master_Abort,
			  Master_Abort => Master_Abort,
			  Clear_Disconnect => Clear_Disconnect,
			  Disconnect_Detected => Disconnect_Detected,
			  Status => SIM_END
	          );

-- instantiate QuickPCI device

    cardbus_5632_1 : cardbus_5632
		port map (ir_n => ir_n,
		          mrs => mrs,
		          or_n => or_n,
		          pae_n => pae_n,
		          paf_n => paf_n,
		          INTAN => INTAN,
		          REQN => REQN,
		          SERRN => SERRN,
		          PERRN => PERRN,
		          PAR => PAR,
		          GNTN => GNTN,
		          STOPN => STOPN,
		          IDSEL => IDSEL,
		          DEVSELN => DEVSELN,
		          RSTN => RSTN,
		          TRDYN => TRDYN,
		          CLK => CLK,
		          IRDYN => IRDYN,
		          FRAMEN => FRAMEN,
		          CBEN => CBEN(3 downto 0),
		          AD => AD(31 downto 0),
		          led => led,
		          lclk => lclk,
		          ren => ren,
		          oe => oe,
		          wen => wen,
		          ld => ld,
		          lad => lad,
		      -- ct added CardBus IP signals
				  pad_CIS_data => pad_CIS_data,
				  pad_BAM => tb_BAM,
				  pad_PWM => tb_PWM,	
				  pad_bvd => tb_bvd,
				  pad_CBLOCK_n	=> tb_CBLOCK_n,
				  pad_clk_resume => tb_clk_resume,
				  pad_gwake => tb_gwake,
				  pad_intr => tb_intr,  
				  pad_ready => tb_ready,
				  pad_wp => tb_wp,
				  pad_CAUDIO => tb_CAUDIO,
				  pad_CINT_n => tb_CINT_n,
				  pad_clk_stopped => tb_clk_stopped,
				  pad_CSTSCHG => tb_CSTSCHG,
				  pad_locked => tb_locked,
				  pad_owner_access => tb_owner_access,
				  pad_CCLKRUN_n => tb_CCLKRUN_n,
	 	          pad_CIS_ADR => pad_CIS_ADR
					);


-- Instantiate the Simulation PCI Master

master1: tf_pci_master
   port map (
              pci_clk => CLK,
              pci_ad => AD,
              pci_cbe => CBEN,
              par => PAR,
              par_64 => PAR64,
              frame_l => FRAMEN,
              irdy_l => IRDYN,
              trdy_l => TRDYN,
              stop_l => STOPN,
              devsel_l => DEVSELN,
              idsel => IDSEL,
              req64_l => REQ64N,
              ack64_l => ACK64N,
              req_l => master1_req_l,
              gnt_l => master1_gnt_l,
              reset_l => RSTN,

              start_bit => master1_start_bit,
              done_bit => master1_done_bit,
              master_addr => master1_addr,
              master_command => master1_command,
			----
              master_addr_parity => '0',
              master_data_parity => '0',

              master_dword_count => master1_dword_count,
              master_initial_data_delay => master1_initial_data_delay,
              master_next_data_delay => master1_next_data_delay,
              master_bad_parity_phase => master1_bad_parity_phase,
              master_m64bit => master1_m64bit,
              master_quiet => master1_quiet,
              be_array => master1_be_array,
              data_array => master1_data_array,
			  pass => master1_pass,
			  last_data  => master1_last_data
         );

master2: tf_pci_master
   port map (
              pci_clk => CLK,
             -- pci_ad => AD,
              pci_cbe => CBEN,
              par => PAR,
              par_64 => PAR64,
              frame_l => FRAMEN,
              irdy_l => IRDYN,
              trdy_l => TRDYN,
              stop_l => STOPN,
              devsel_l => DEVSELN,
              --idsel => IDSEL,
              req64_l => REQ64N,
              ack64_l => ACK64N,
              req_l => master2_req_l,
              gnt_l => master2_gnt_l,
              reset_l => RSTN,

              start_bit => master2_start_bit,
              done_bit => master2_done_bit,
              master_addr => master2_addr,
              master_command => master2_command,
			----
              master_addr_parity => '0',
              master_data_parity => '0',

              master_dword_count => master2_dword_count,
              master_initial_data_delay => master2_initial_data_delay,
              master_next_data_delay => master2_next_data_delay,
              master_bad_parity_phase => master2_bad_parity_phase,
              master_m64bit => master2_m64bit,
              master_quiet => master2_quiet,
              be_array => master2_be_array,
              data_array => master2_data_array,
			  pass => master2_pass,
			  last_data  => master2_last_data
         );
-- Instantiate the Simulation PCI Target

    target1 : pci_tar

     generic map (MEM_SIZE =>  target1_MEMSIZE,
		          BUS_SIZE =>  target1_BUS_SIZE
				  )

        port map (clk => CLK,
		          pci_ad => AD,
		          c_be_n => CBEN,
		          par => PAR,
		          par64 => PAR64,
		          frame_n => FRAMEN,
		          irdy_n => IRDYN,
		          trdy_n => TRDYN,
		          devsel_n => DEVSELN,
		          req64_n => REQ64N,
		          ack64_n => ACK64N,
		          rst_n => RSTN,
		          stop_n => STOPN,
		          perr_n => PERRN,
		          RANDOM_VAL =>  target1_RANDOMVAL,
		          DEVICE_SPEED =>  target1_DEVICE_SPEED,
		          BASE_ADDRESS =>  target1_BASE_ADDRESS,
		          STOP_COUNT =>  target1_STOP_COUNT,
		          STOP_ENABLE =>  target1_STOP_ENABLE,
		          WAITSTATES_ENABLE =>  target1_WAITSTATES_ENABLE,
		          VARIABLE_WAITS =>  target1_VARIABLE_WAITS,
		          MAX_WAITS =>  target1_MAX_WAITS,
		          MIN_WAITS =>  target1_MIN_WAITS,
		          INITIAL_WAITS =>  target1_INITIAL_WAITS,
		          SUBSEQUENT_WAITS =>  target1_SUBSEQUENT_WAITS,
		          STOP_WAITS =>  target1_STOP_WAITS,
		          RETRY_COUNT =>  target1_RETRY_COUNT,
		          ENABLE_RETRY_COUNT =>  target1_ENABLE_RETRY_COUNT,
		          WRONG_PAR =>  target1_WRONG_PAR,
		          WRONG_PAR64 =>  '0',
		          PERR_ASSERT =>  target1_PERR_ASSERT,
		          TARGET_ABORT =>  target1_TARGET_ABORT
		          );

-- Instantiate the Simulation PCI Arbiter

    arbiter : pci_arbiter
		generic map (PCI_MASTER_DEVICES =>  PCI_MASTER_DEVICES
		)
		port map (pci_clk => CLK,
		          request_n(2) => REQN,
  			  request_n(1) => master2_req_l,
  --					request_n(1) => REQN,
				  request_n(0) => master1_req_l,
		          grant_n(2) => GNTN,
	--				grant_n(1) => GNTN,
	  			  grant_n(1) => master2_gnt_l,
				  grant_n(0) => master1_gnt_l,
		          busy => busy,
		          reset_n => RSTN);

	busy <= not(FRAMEN AND IRDYN);

-- Drive the PCI Reset and Clock Signals

pci_clk_proc: process is begin
	CLK <= '0';
	wait for 31 ns;
	wait for skew;
	CLK <= '1';