ram128x18_25um.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

------------------------------------------------------------------------
-- File : RAM128X18_25UM.vhd
-- Design Date: 9 Feb 00
-- Creation Date: Tue May 07 10:53:25 2002
-- Created By SpDE Version: SpDE 9.3 Alpha Build3
-- Authors: Brian Faith, Ed Bezeg, QuickLogic Corporation,
-- Copyright (C) 2000, Customers of QuickLogic may use this
-- file for use in designing QuickLogic devices only.
-- Description : VHDL RAM Model for 128x18, .25um RAM block.
-- Synchronous Write, both Synchronous and Asynchronous Read
------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity RAM128X18_25UM is
  port (WA, RA : in std_logic_vector (6 downto 0);
        WD : in std_logic_vector (17 downto 0);
        WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
        RD : out std_logic_vector (17 downto 0) );

  attribute syn_isclock : boolean;
  attribute syn_isclock of WCLK : signal is true;
  attribute syn_isclock of RCLK : signal is true;

end RAM128X18_25UM;

architecture arch of RAM128x18_25um is

attribute syn_black_box : boolean;
attribute syn_black_box of arch : architecture is true;

signal RAREG : std_logic_vector (6 downto 0) := "0000000";
signal RADDR : std_logic_vector (6 downto 0);
type memory_type is array (integer range <>) of std_logic_vector (17 downto 0);
signal mem : memory_type (0 to 127);

begin

WRITE : process (WCLK)
begin
   if Rising_Edge(WCLK) then       	     
      if (WE = '1') then
         mem(CONV_INTEGER(WA)) <= WD ;
      end if;
   end if;
end process;

READ : process (RCLK)
begin
   if Rising_Edge(RCLK) then
      if (RE = '1') then
         RAREG <= RA ;
      else
         RAREG <= RAREG ;
      end if;
   end if;
end process;

assign_rd : process (RADDR, mem)
begin
   RD <= mem(CONV_INTEGER(RADDR)) ;
end process;
RADDR <= RA when (ASYNCRD = '1') else RAREG ;

end arch;