📄 pci_arb.tb
字号:
--------------------------------------------------------------------------------
--
-- File : pci_arb.tb
-- Last Modification: 07/19/2001
--
-- Created In SpDE Version: SpDE 8.22
-- Author : Richard Yuan, QuickLogic Corporation
-- Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--
-- Description :
-- This is a PCI arbiter model.
-- Please see "The QL5064 PCI Bus Simulation Environment" for detailed informaiton.
--
-- Hierarchy:
-- The pci_arbiter entity is to be used in pci5(3/4)32_208.tb.
--
-- History:
-- Date Author Version
-- 06/26/01 Richard Yuan 1.0
-- - Header reorganized to conform to coding standard.
-- 07/19/01 Richard Yuan 1.1
-- - Initial value added for grant_device and search_device.
--------------------------------------------------------------------------------
--PARAMETER PCI_MASTER_DEVICES DEFAULT 1
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY pci_arbiter IS
GENERIC (PCI_MASTER_DEVICES : integer := 1);
PORT (
pci_clk : IN std_logic;
request_n : IN std_logic_vector(PCI_MASTER_DEVICES-1 downto 0);
grant_n : OUT std_logic_vector(PCI_MASTER_DEVICES-1 downto 0);
busy : IN std_logic;
reset_n : IN std_logic
);
END pci_arbiter;
ARCHITECTURE pci_arbiter_ARC_CORE OF pci_arbiter IS
CONSTANT OUTPUT_DELAY : time := 2 NS;
--------Initial value signals
SIGNAL grant_reg : std_logic_vector(PCI_MASTER_DEVICES-1 downto 0) := (others=>'0');
-- OUTPUT SIGNALS (TEMPS)
SIGNAL grant_n_outtmp : std_logic_vector(PCI_MASTER_DEVICES-1 downto 0);
-- Wires -> SIGNALs
SIGNAL request : std_logic_vector(PCI_MASTER_DEVICES-1 downto 0);
SIGNAL reset : std_logic;
-- Regs -> SIGNALs
SIGNAL grant_device : integer := 0;
BEGIN
-- The Assigns for the Output Vars
grant_n <= grant_n_outtmp;
-- The Assigns for the temp Vars
--Beginning of actual code
reset <= NOT reset_n;
grant_n_outtmp(PCI_MASTER_DEVICES-1 downto 0) <= (others=>'0') WHEN reset = '1' ELSE NOT grant_reg(PCI_MASTER_DEVICES-1 downto 0) after OUTPUT_DELAY;
request(PCI_MASTER_DEVICES-1 downto 0) <= (others=>'Z') WHEN reset = '1' ELSE NOT request_n(PCI_MASTER_DEVICES-1 downto 0);
--ALWAYS: posedge pci_clk or posedge reset) begin if (reset) begin grant_device <= 0
arbiter: PROCESS ( pci_clk, reset)
VARIABLE idle : std_logic;
VARIABLE NEXT_DEVICE : std_logic := '0';
VARIABLE search_device : integer := 0;
VARIABLE jptempvar3 : std_logic;
BEGIN
IF reset = '1' THEN
grant_device <= 0;
idle := '0';
grant_reg(PCI_MASTER_DEVICES-1 downto 1) <= (others=>'0');
grant_reg(0) <= '1';
--ADDED IF BELOW
ELSIF rising_edge(pci_clk) THEN
IF idle = '1' THEN
grant_reg(grant_device) <= '1';
idle := '0';
ELSE
IF (NOT (request(grant_device))) = '1' THEN
NEXT_DEVICE := '1';
END IF;
-------jptempvar2 <= '1' WHEN grant_device = PCI_MASTER_DEVICES-1 ELSE '0';
IF NEXT_DEVICE = '1' THEN
IF grant_device = PCI_MASTER_DEVICES-1 THEN
search_device := 0;
ELSE
search_device := grant_device + 1;
END IF;
-----jptempvar3 <= '1' WHEN search_device = grant_device ELSE '0';
IF search_device = grant_device THEN
jptempvar3 := '1';
ELSE jptempvar3 := '0';
END IF;
WHILE ((NOT request(search_device)) AND (NOT jptempvar3)) = '1' LOOP
IF (search_device = (PCI_MASTER_DEVICES - 1)) THEN
search_device := 0;
ELSE
search_device := search_device + 1;
END IF;
IF search_device = grant_device THEN
jptempvar3 := '1';
ELSE jptempvar3 := '0';
END IF;
END LOOP;
-----jptempvar3 <= '1' WHEN search_device = grant_device ELSE '0';
IF search_device = grant_device THEN
ELSE
NEXT_DEVICE := '0';
grant_reg(grant_device) <= '0';
grant_device <= search_device;
IF busy = '1' THEN
grant_reg(search_device) <= '1';
ELSE
idle := '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END pci_arbiter_ARC_CORE;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -