pci_pack.tb

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

--------------------------------------------------------------------------------
--
-- File : pci_pack.tb
-- Last Modification: 06/26/2001
--
-- Created In SpDE Version: SpDE 8.22
-- Author :	Richard Yuan, QuickLogic Corporation
-- Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--	
-- Description :
--	Defines functions and data types for use in the PCI test bench.
--
-- Hierarchy:
--	This file provides a package to be used in pci5(3/4)32_208.tb.
--
-- History:	
--	Date	        Author					Version
--  06/26/01		Richard Yuan			1.0
--		- Header reorganized to conform to coding standard.
--
--------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

PACKAGE pci_pack IS
FUNCTION Unary_XOR(the_var: std_logic_vector) return std_logic;
FUNCTION vec2str(vec: std_logic_vector) return string;
function vec2hstr (vec: std_logic_vector) return string;
TYPE BYTE_ARRAY_TYPE is array (0 to 4095) of std_logic_vector(3 downto 0);
TYPE DATA_ARRAY_TYPE is array (0 to 4095) of std_logic_vector(31 downto 0);

constant log_file : string := "test_result.log";

constant MEM_SIZE : integer := 16384;
TYPE MEMORY_ARRAY_TYPE is array (0 to MEM_SIZE-1) of std_logic_vector(7 downto 0);

TYPE PCI_SPACE_TYPE is (CFG, MEM, IO);
TYPE MASTER_CTRL_TYPE is record
	initial_waits : integer;
	subsequent_waits : integer;
	bad_parity_phase : integer;
	quiet : std_logic;
end record;	
TYPE MASTER_REQ_TYPE is record
	start : std_logic;
	addr  : std_logic_vector (63 downto 0);
	command : std_logic_vector (3 downto 0);
	dword_count : integer;
	m64bit : std_logic;
	be_array : BYTE_ARRAY_TYPE;
	data_array : DATA_ARRAY_TYPE;
end record;	
TYPE MASTER_RESP_TYPE is record	   
	done : std_logic;
	pass : std_logic;
	last_data : std_logic_vector (63 downto 0);
	CLK : std_logic;
end record;	  

type gpio_command is (INITIALIZE,LED_TEST,SW_DIP_TEST,CAM_LINK_TEST,CAM_LINK_M_TEST);

constant cLOCAL_CLOCK_PERIOD : time := 20.000 ns;    
constant HalfCyclePCI : time := 15 ns;
constant skew : time := 3 ns;
constant Tgnt         : time :=  6.0 ns;
constant cHW_RST_WIDTH : time := 100 ns;
--constant cHW_RST_WIDTH : time := 30 us;         
constant cCLK1A_DLY : time := 0 ns;
constant cCLK2_DLY : time := 0 ns;
constant cCLK_OUT1_DLY : time := 0.5 ns;
constant cCLK_P_DLY : time := 0.5 ns;
constant cLVDS_DLY    : time := 2.0 ns;   

constant DUT_IDSEL_ADDR : std_logic_vector(31 downto 0) := X"4000_0000";
constant DUT_BAR0       : std_logic_vector(31 downto 0) := X"8000_0000";
constant HOST_BAR0      : std_logic_vector(31 downto 0) := X"0100_0000";

constant cDMA_LEN             : std_logic_vector(31 downto 0) := X"0000_01A0";
constant cDMA_LEN_DDR         : std_logic_vector(31 downto 0) := X"0000_0013";
constant cDMA_CNT_LEN_DDR     : std_logic_vector(31 downto 0) := X"0100_0423";
constant TX_START_POINTER  : std_logic_vector (31 downto 0) := X"0000_0000";
constant RX_START_POINTER  : std_logic_vector (31 downto 0) := X"0000_2000";
--constant RX_START_POINTER  : std_logic_vector (31 downto 0) := X"0000_0800";
constant DMA_READ_CONTROL  : std_logic_vector (31 downto 0) := X"0002_1636";
constant DMA_WRITE_CONTROL : std_logic_vector (31 downto 0) := X"0002_1677";
constant DMA_DDR_READ_CONTROL  : std_logic_vector (31 downto 0) := X"0002_17B6";
constant DMA_DDR_WRITE_CONTROL : std_logic_vector (31 downto 0) := X"0002_17F7";  
constant SDRAM_START_ADDRESS : std_logic_vector (31 downto 0) := X"003F_FFF0";


constant CFG_CSR  : std_logic_vector(31 downto 0) := X"0000_0004";
constant CFG_REV  : std_logic_vector(31 downto 0) := X"0000_0008";
constant CFG_LAT  : std_logic_vector(31 downto 0) := X"0000_000C";
constant CFG_BAR0 : std_logic_vector(31 downto 0) := X"0000_0010";
constant CFG_BAR1 : std_logic_vector(31 downto 0) := X"0000_0014";
constant CFG_BAR2 : std_logic_vector(31 downto 0) := X"0000_0018";
constant CFG_SUB  : std_logic_vector(31 downto 0) := X"0000_002C";


--// PCI COMMAND CODES //
constant  INTERRUPT_ACK  : std_logic_vector(3 downto 0) := "0000";
constant  SPECIAL_CYCLE  : std_logic_vector(3 downto 0) := "0001";
constant  IO_READ        : std_logic_vector(3 downto 0) := "0010";
constant  IO_WRITE       : std_logic_vector(3 downto 0) := "0011";
constant  CMD_RESERVED_1 : std_logic_vector(3 downto 0) := "0100";
constant  CMD_RESERVED_2 : std_logic_vector(3 downto 0) := "0101";
constant  MEM_READ       : std_logic_vector(3 downto 0) := "0110";
constant  MEM_WRITE      : std_logic_vector(3 downto 0) := "0111";
constant  CMD_RESERVED_3 : std_logic_vector(3 downto 0) := "1000";
constant  CMD_RESERVED_4 : std_logic_vector(3 downto 0) := "1001";
constant  CONFIG_READ    : std_logic_vector(3 downto 0) := "1010";
constant  CONFIG_WRITE   : std_logic_vector(3 downto 0) := "1011";
constant  MEM_READ_MULT  : std_logic_vector(3 downto 0) := "1100";
constant  DUAL_ADDR      : std_logic_vector(3 downto 0) := "1101";
constant  MEM_READ_LINE  : std_logic_vector(3 downto 0) := "1110";
constant  MEM_WR_INVALID : std_logic_vector(3 downto 0) := "1111";

END pci_pack;

PACKAGE BODY pci_pack IS

FUNCTION Unary_XOR(the_var: std_logic_vector) return std_logic IS
VARIABLE temp_value_holder : std_logic;
BEGIN
   temp_value_holder := '0';
   FOR mover IN the_var'high downto the_var'low LOOP
      IF the_var(mover)='Z' OR the_var(mover)='X' OR the_var(mover)='U' THEN
         RETURN 'X';
      ELSIF the_var(mover) = '1' THEN
         temp_value_holder := NOT temp_value_holder;
      END IF;
   END LOOP;
   RETURN temp_value_holder;
end Unary_XOR;

FUNCTION vec2str(vec: std_logic_vector) return string is

alias veca : std_logic_vector(1 to vec'length) is vec;
variable stmp : string(2 to vec'length+1);
begin
   for i in veca'reverse_range loop
      if (veca(i) = 'U') then
         stmp(i+1) := 'U';
      elsif (veca(i) = 'X') then
         stmp(i+1) := 'X';
      elsif (veca(i) = '0') then
         stmp(i+1) := '0';
      elsif (veca(i) = '1') then
         stmp(i+1) := '1';
      elsif (veca(i) = 'Z') then
         stmp(i+1) := 'Z';
      elsif (veca(i) = 'W') then
         stmp(i+1) := 'W';
      elsif (veca(i) = 'L') then
         stmp(i+1) := 'L';
      elsif (veca(i) = 'H') then
         stmp(i+1) := 'H';
      else
         stmp(i+1) := '-';
      end if;
   end loop;
   return stmp;
end;



function vec2hstr (vec: std_logic_vector) return string is
	alias veca : std_logic_vector(vec'length downto 1) is vec;
	variable return_string : string((vec'length / 4) downto 1);
	variable i : integer;
	variable nibble : std_logic_vector(4 downto 1);
begin
	i := 1;
	while (i <= vec'length) loop
		nibble := veca(i+3 downto i);
		case nibble is
			when "0000" => return_string((i+3)/4) := '0';
			when "0001" => return_string((i+3)/4) := '1';
			when "0010" => return_string((i+3)/4) := '2';
			when "0011" => return_string((i+3)/4) := '3';
			when "0100" => return_string((i+3)/4) := '4';
			when "0101" => return_string((i+3)/4) := '5';
			when "0110" => return_string((i+3)/4) := '6';
			when "0111" => return_string((i+3)/4) := '7';
			when "1000" => return_string((i+3)/4) := '8';
			when "1001" => return_string((i+3)/4) := '9';
			when "1010" => return_string((i+3)/4) := 'A';
			when "1011" => return_string((i+3)/4) := 'B';
			when "1100" => return_string((i+3)/4) := 'C';
			when "1101" => return_string((i+3)/4) := 'D';
			when "1110" => return_string((i+3)/4) := 'E';
			when "1111" => return_string((i+3)/4) := 'F';
			when others => return_string((i+3)/4) := 'X';
		end case;
		i := i+4;
	end loop;
	return return_string;
end;



end pci_pack;