pci_mast.tb

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

------jptempvar45 <=  '1' WHEN countleft = jptempvar46 ELSE '0';
------jptempvar46 <=  BASETEN2 WHEN m64bit = '1'  ELSE  BASETEN1;
              ---- Deassert frame when a stop is signaled or no more than 1 data phase left
              IF m64bit = '1' THEN
                 jptempvar46 := 2;
              ELSE
                 jptempvar46 := 1;
              END IF;
              IF countleft = jptempvar46 THEN
                 jptempvar45 := '1';
              ELSE
                 jptempvar45 := '0';
              END IF;
              IF (jptempvar45 OR stop) = '1' THEN
                 frame_reg <=  '0'; -- data to transfer for one clock
                 frame_oe <=  '0';
              END IF;
           END IF;
        END IF;

        ---- This is the end of the last data phase! Disable outputs
        IF ((NOT frame) AND (irdy AND (trdy OR stop))) = '1' THEN
           ---- Disable the address and command busses
           pci_ad_oe <=  '0';
           pci_cbe_oe <=  '0';
           idsel_oe <=  '0'; -- idsel is not invalid, this line should be removed
           irdy_oe <=  '0';
           req64_oe <=  '0';
           IF  (NOT hold_req) = '1' THEN
              req_reg <=  '0';
           END IF;
           quit :=  '1';
        END IF;

        --- invert the command bus to get the correct byte selects
        IF m64bit = '1' THEN
           pci_cbe_reg(7 downto 0) <= NOT (be_array(index+1) & be_array(index));
        ELSE
           --- Set byte enable turned off on upper 32 bits
           pci_cbe_reg(7 downto 0) <= NOT ("0000" & be_array(index));
        END IF;
    END LOOP; --- end while !quit

    --- for the turn-around cycle
    IF (stop AND (NOT trdy)) = '1' THEN
      wait until rising_edge(pci_clk);
    END IF;

END target_access_one_frame;


procedure target_access(SIGNAL address : IN std_logic_vector(63 downto 0);
                        command : IN std_logic_vector(3 downto 0);
                        addr_parity : IN std_logic;
                        data_parity : IN std_logic;
                        SIGNAL dword_count : IN integer;
                        initial_data_delay : IN integer;
                        next_data_delay : IN integer;
                        SIGNAL m64bit : IN std_logic;
                        SIGNAL data_array : IN DATA_ARRAY_TYPE;
                        SIGNAL be_array   : IN BYTE_ARRAY_TYPE;
                        SIGNAL req_reg : INOUT std_logic;
                        SIGNAL irdy_reg : INOUT std_logic;
                        SIGNAL frame_oe : OUT std_logic;
                        SIGNAL frame_reg : INOUT std_logic;
                        SIGNAL idsel_oe : OUT std_logic;
                        SIGNAL pci_ad_oe : OUT std_logic;
                        SIGNAL pci_cbe_oe : OUT std_logic;
                        SIGNAL pci_ad_reg : OUT std_logic_vector(63 downto 0);
                        SIGNAL pci_cbe_reg : OUT std_logic_vector(7 downto 0);
                        SIGNAL idsel_reg : OUT std_logic;
                        SIGNAL req64_oe : OUT std_logic;
                        SIGNAL irdy_oe : OUT std_logic;
                        SIGNAL pass : OUT std_logic;
                        SIGNAL last_data : OUT std_logic_vector(63 downto 0)
						

                        ) IS
VARIABLE pass_fail : std_logic;
VARIABLE m64_local   : std_logic;
VARIABLE got_devsel   : std_logic;
VARIABLE array_position   : integer;
VARIABLE dwords_transmitted   : integer;
VARIABLE jptempvar30   : std_logic;
VARIABLE jptempvar90   : std_logic;
VARIABLE jptempvar91   : std_logic;
VARIABLE last_data_var : std_logic_vector(63 downto 0);
VARIABLE local_address   : std_logic_vector(63 downto 0);
VARIABLE local_dword_count   : integer;
BEGIN
   local_address := address;
   local_dword_count := dword_count;
   pass_fail :=  '1';
          ----------jptempvar30 <=  '1' WHEN 
           ----------( dword_count(31 downto 0) )  <  1  ELSE '0';
   ASSERT (local_dword_count >= 1)
      REPORT "ERROR: target_access requested with a transfer count of 0"
      SEVERITY Failure;
     -------   HELP(repeat (10) @(posedge pci_clk));

   IF force_32 = '1' THEN
       m64_local := '0';
   ELSE
       m64_local := m64bit;
   END IF;

   got_devsel := '1';
   array_position := 0;
   IF local_dword_count > 0 THEN jptempvar30 :=  '1';
     ELSE jptempvar30 := '0';  END IF;
   WHILE (got_devsel AND jptempvar30) = '1' LOOP
       dwords_transmitted := 0;
       IF local_address(2 downto 0) = "000" THEN jptempvar90 := '1';
          ELSE jptempvar90 := '0'; END IF;
       IF (local_dword_count mod 2) = 0 THEN jptempvar91 := '1';
          ELSE jptempvar91 := '0'; END IF;
       target_access_one_frame(address=>local_address, command=>command,
                addr_parity=>addr_parity, data_parity=>data_parity,
                burst_count=>local_dword_count, initial_data_delay=>initial_data_delay,
                next_data_delay=>next_data_delay,
                m64bit_in=>m64_local AND (jptempvar90 AND jptempvar91),
                initial_array_position=>array_position,
                pass_fail=>pass_fail, quiet=>master_quiet, last_data=>last_data_var, hold_req=>'0',
   ----- The following are being passed in so the can be driven
                req_reg=>req_reg, irdy_reg=>irdy_reg, frame_oe=>frame_oe,
                frame_reg=>frame_reg, idsel_oe=>idsel_oe, pci_ad_oe=>pci_ad_oe,
                pci_cbe_oe=>pci_cbe_oe, pci_ad_reg=>pci_ad_reg, pci_cbe_reg=>pci_cbe_reg,
                idsel_reg=>idsel_reg, req64_oe=>req64_oe, irdy_oe=>irdy_oe,
                got_devsel=>got_devsel, dwords_transmitted=>dwords_transmitted,
                fake_a_DAC=>fake_a_DAC
                );
       array_position := array_position + dwords_transmitted;
       local_address(63 downto 0) := std_logic_vector(unsigned(local_address(63 downto 0)) + to_unsigned((dwords_transmitted * 4),64)) ;
       local_dword_count := local_dword_count - dwords_transmitted;
       IF local_dword_count > 0 THEN jptempvar30 :=  '1';
         ELSE jptempvar30 := '0';  END IF;
   END LOOP;
   pass <= pass_fail;
   last_data <= last_data_var;
end target_access;



 


BEGIN
--------THIS is the process which calls the procedure each time start_bit is pulsed
start_bit_process: PROCESS
BEGIN
   wait until rising_edge(start_bit);
   done_bit <= '0';

   target_access(address => master_addr,
                 command => master_command,
                 addr_parity => master_addr_parity,
                 data_parity => master_data_parity,
                 dword_count => master_dword_count,
                 initial_data_delay => master_initial_data_delay,
                 next_data_delay => master_next_data_delay,
                 m64bit => master_m64bit,
                 data_array => data_array,
                 be_array => be_array,
                 req_reg=>req_reg, irdy_reg=>irdy_reg, frame_oe=>frame_oe,
                 frame_reg=>frame_reg, idsel_oe=>idsel_oe, pci_ad_oe=>pci_ad_oe,
                 pci_cbe_oe=>pci_cbe_oe, pci_ad_reg=>pci_ad_reg,
                 pci_cbe_reg=>pci_cbe_reg,
                 idsel_reg=>idsel_reg, req64_oe=>req64_oe, irdy_oe=>irdy_oe, pass=>pass,
                 last_data => last_data);
   done_bit <= '1';
END PROCESS;


-- The Assigns for the Output Vars
req_l   <= req_l_outtmp;
req64_l   <= req64_l_outtmp;
pci_cbe(7 downto 0)   <= pci_cbe_outtmp(7 downto 0);

-- The Assigns for the temp Vars

--Beginning of actual code


  pci_ad(63 downto 0) <=  pci_ad_reg(63 downto 0) after OUTPUT_DELAY WHEN  ( pci_ad_oe )  = '1'  ELSE  "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" after OUTPUT_DELAY;
  pci_cbe_outtmp(7 downto 0) <=  pci_cbe_reg(7 downto 0) after OUTPUT_DELAY WHEN  ( pci_cbe_oe )  = '1'  ELSE  "ZZZZZZZZ" after OUTPUT_DELAY;
  frame_l <=   NOT frame_reg after OUTPUT_DELAY WHEN  ( frame_oe )  = '1'  ELSE  'Z' after OUTPUT_DELAY;
  irdy_l <=   NOT irdy_reg after OUTPUT_DELAY WHEN  ( irdy_oe )  = '1'  ELSE  'Z' after OUTPUT_DELAY;
  idsel <=  idsel_reg after OUTPUT_DELAY WHEN  ( idsel_oe )  = '1'  ELSE  'Z' after OUTPUT_DELAY;
  frame <=  NOT frame_l;
  irdy <=  NOT irdy_l;
  trdy <=  NOT trdy_l;
  devsel <=  NOT devsel_l;
  stop <=  NOT stop_l;
  reset <=  NOT reset_l;
  gnt <=  NOT gnt_l;
  req_l_outtmp <=  '1' after OUTPUT_DELAY WHEN  ( reset )  = '1'  ELSE   (  NOT req_reg ) after OUTPUT_DELAY;
  local_req64_l <=  '0' after OUTPUT_DELAY WHEN  ( req64_oe AND  frame_oe )  = '1'  ELSE  'Z' after OUTPUT_DELAY;
  disconnect_req64 <= '0';
  fake_a_DAC <= '0';
  req64_l_outtmp <=  '1' WHEN  ( disconnect_req64 )  = '1'  ELSE  local_req64_l;

--ALWAYS: negedge reset) begin     if (req64_l == 1'b1) force_32 = 1'b1
force32_assign: PROCESS ( reset)
BEGIN
----jptempvar0 <=  '1' WHEN 
---- ( req64_l_outtmp )  =  (  '1' )  ELSE '0';
  IF falling_edge(reset) THEN
   IF req64_l_outtmp = '1' THEN
      force_32 <= '1';
   END IF;
  END IF;
END PROCESS;

par64_reg_with_error <= par64_reg;
perr64_injected <= par64_reg_with_error XOR par64_reg;
perr_injected <= par_reg_with_error XOR par_reg;
--par_reg_with_error <= par_reg;
par_reg_with_error <= not par_reg when (phase_count = master_bad_parity_phase) else par_reg;

par <= par_reg_with_error after OUTPUT_DELAY WHEN par_oe_reg = '1' ELSE 'Z' after OUTPUT_DELAY;
par_64 <= par64_reg_with_error after OUTPUT_DELAY WHEN par64_oe_reg = '1' ELSE  'Z' after OUTPUT_DELAY;

parity_errors: PROCESS (pci_clk)
BEGIN
   IF rising_edge(pci_clk) THEN
      IF (par_oe_reg = '1') THEN
         ASSERT (NOT (par_reg_with_error = 'X'))
            REPORT "ERROR: parity output from ext_master is X"
            SEVERITY ERROR;
      END IF;
      IF (par64_oe_reg = '1') THEN
         ASSERT (NOT (par64_reg_with_error = 'X'))
            REPORT "ERROR: parity 64 output from ext_master is X"
            SEVERITY ERROR;
      END IF;
   END IF;
END PROCESS;
 
----always @(posedge pci_clk or negedge reset_l) if ( ~reset_l ) begin 		par_reg ) <=  '0';
parity_assign: PROCESS (pci_clk, reset_l)
BEGIN
   IF (NOT reset_l) = '1' THEN
      par_reg <=  '0';
      par_oe_reg <=  '0';
      par64_reg <=  '0';
      par64_oe_reg <=  '0';
      frame_dly <=  '0';
      irdy_dly <=  '0';
      irdy_oe_dly <=  '0';
   ELSIF rising_edge(pci_clk) THEN
      par_oe_reg <=  pci_ad_oe;
      par64_oe_reg <=  pci_ad_oe;
      frame_dly <=  frame;
      irdy_dly <=  irdy;
      irdy_oe_dly <=  irdy_oe;
      IF  ((frame AND (NOT frame_dly)) OR ((NOT frame) AND (NOT irdy))) = '1' THEN
         phase_count <=  1;
      --ELSIF (trdy OR (frame AND (NOT irdy))) = '1' THEN
      ELSIF (trdy AND irdy) = '1' THEN
         phase_count <=  phase_count + 1;
      END IF;
      par_reg <= Unary_XOR(pci_ad(31 downto 0)) XOR Unary_XOR(pci_cbe_outtmp(3 downto 0));
      par64_reg <= Unary_XOR(pci_ad(63 downto 32)) XOR Unary_XOR(pci_cbe_outtmp(7 downto 4));
	  master_bad_parity_phase_dly <= master_bad_parity_phase;
	  if phase_count = master_bad_parity_phase_dly then
		 --master_bad_parity_phase <= 0;
		 master_bad_parity_phase_dly <= 0;		        
      end if;
   END IF;
END PROCESS;

bus_idle_ready_to_start <=  ((NOT irdy) AND (NOT frame)) OR (irdy AND ((trdy OR stop) AND ((NOT frame) AND irdy_oe)));


END tf_pci_master_ARC_CORE;