pci_mast.tb

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

                                  SIGNAL req64_oe : OUT std_logic;
                                  SIGNAL irdy_oe : OUT std_logic;
                                  VARIABLE got_devsel : INOUT std_logic;
                                  VARIABLE dwords_transmitted : INOUT integer;
                                  SIGNAL fake_a_DAC : IN std_logic) IS
VARIABLE timeleft   : integer;
VARIABLE countleft   : integer;
VARIABLE timeout   : integer;
VARIABLE quit : std_logic;
VARIABLE burst : std_logic;
VARIABLE jptempvar33   : std_logic;
VARIABLE jptempvar34   : std_logic;
VARIABLE jptempvar35   : std_logic;
VARIABLE jptempvar37   : integer;
VARIABLE jptempvar38   : std_logic;
VARIABLE jptempvar39   : integer;
VARIABLE jptempvar40   : std_logic;
VARIABLE jptempvar41   : std_logic;
VARIABLE jptempvar44   : std_logic;
VARIABLE jptempvar45   : std_logic;
VARIABLE jptempvar46   : integer;
VARIABLE index   : integer;
VARIABLE data_read   : std_logic_vector(63 downto 0);
VARIABLE m64bit : std_logic;
BEGIN
----jptempvar32 <=  '1' WHEN 
 ----( burst_count(63 downto 0) )  <  (  BASETEN1 )  ELSE '0';
 ---- jptempvar32
    ASSERT (burst_count >= 1)
       REPORT "ERROR: target_access requested with a transfer count of 0"
       SEVERITY Failure;
      -------   HELP(repeat (10) @(posedge pci_clk));

    IF (initial_array_position >= 0) THEN
       ASSERT (initial_array_position <= RW_BUFF_SIZE)
         REPORT "ERROR: intial_array_position in ext_master out of range (>RW_BUFF_SIZE)"
         SEVERITY Failure;
    ELSE
       ASSERT (False)
         REPORT "ERROR: initial_array_position in ext_master out of range (< 0)"
         SEVERITY Failure;
    END IF;
    
    m64bit := m64bit_in;
    req_reg <=  '1';
      ---- Get the grant before commencing
    IF ((NOT (req_reg AND gnt)) OR (NOT bus_idle_ready_to_start)) = '1' THEN
        req_reg <= '1';
      wait until rising_edge(pci_clk);
        WHILE ((NOT gnt) OR (NOT bus_idle_ready_to_start)) = '1' LOOP
          wait until rising_edge(pci_clk);
        END LOOP;
    END IF;

    irdy_reg <= '0';
       ------Initialize the delay and counter variables
    timeleft := initial_data_delay + 1;
    countleft :=  burst_count;
    timeout :=  0;
    got_devsel :=  '0';
    quit :=  '0';
       ---- From now on, everything will be treated as a burst
    burst :=  '1';

      --- Assert frame
    frame_oe <= '1';
    frame_reg <= '1';

      --- Assert idsel (???)
    idsel_oe <=  '1';
    IF command(3 downto 0) = "1010" THEN
       jptempvar33 :=  '1';
    ELSE
       jptempvar33 := '0';
    END IF;
    IF command(3 downto 0) = "1011" THEN
       jptempvar34 :=  '1';
    ELSE
       jptempvar34 := '0';
    END IF;
    IF  (  ( jptempvar33 )  OR  (  jptempvar34 )  )  = '1'  THEN
        idsel_reg <=  '1';
    ELSE
        idsel_reg <=  '0';
    END IF;

       ---- Enable the address and command busses
    pci_ad_oe <=  '1';
    pci_cbe_oe <=  '1';
       ---- Set the 64 bit request line if we are a 64bit master
    req64_oe <=  m64bit;


   ---- Split address and add a clock cycle if we have a 64 bit addres
    IF address(63 downto 32) = "00000000000000000000000000000000" THEN
       jptempvar35 :=  '1';
    ELSE
       jptempvar35 := '0';
    END IF;
    IF  ((NOT jptempvar35) OR fake_a_DAC) = '1' THEN
        pci_ad_reg(63 downto 0) <=  address(63 downto 0);
        pci_cbe_reg(7 downto 0) <=   ( command(3 downto 0)
              & "1101");   --THIS IS CONCATENATION
      wait until rising_edge(pci_clk);
        pci_ad_reg(63 downto 0) <=   ( address(63 downto 32) & address(63 downto 32));
        pci_cbe_reg(7 downto 0) <= (command(3 downto 0) & command(3 downto 0) ) ;
    ELSE
        ---- Otherwise, set the address and command values
        pci_ad_reg(63 downto 0) <=   ( "00000000000000000000000000000000" & address(31 downto 0));
        IF m64bit = '1' THEN
           pci_cbe_reg(7 downto 0) <= (command(3 downto 0) & command(3 downto 0));
        ELSE
           pci_cbe_reg(7 downto 0) <= ("0000" & command(3 downto 0));
        END IF;
    END IF;

       ------- INSERT PARITY CHECK HERE

      -- assert irdy
    irdy_oe <=  '1';
    WHILE (NOT quit) = '1' LOOP
      wait until rising_edge(pci_clk);
          --- Stop requesting if we see stop asserted
        IF stop = '1'  THEN
           req_reg <=  '0';
        END IF;
           --- Remember if we saw devsel
        IF devsel = '1'  THEN
           got_devsel :=  '1';
        END IF;

           --- set the current index into the data_array
        index := initial_array_position + (burst_count - countleft);


---jptempvar37 <=  timeout(15 downto 0) WHEN  ( jptempvar38 )  = '1'  ELSE  timeout(15 downto 0) +  BASETEN1;
---jptempvar38 <=  '1' WHEN 
 ---( timeout(15 downto 0) )  >  (  BASETEN15 )  ELSE '0';
---jptempvar39 <=  BASETEN0 WHEN  (  ( jptempvar40 )  )  = '1'  ELSE  timeleft(5 downto 0) -  BASETEN1;
---jptempvar40 <=  '1' WHEN 
 ---( timeleft(5 downto 0) )  =  (  BASETEN0 )  ELSE '0';



        IF timeout > 15 THEN
            jptempvar37 := timeout;
        ELSE
            jptempvar37 := timeout + 1;
        END IF;
  --- Update timeout (counts up to 15, devsel must be seen before 10)
        timeout := jptempvar37;


        IF timeleft = 0 THEN
            jptempvar39 := 0;
        ELSE
            jptempvar39 := timeleft - 1;
        END IF;
  --- Update time left (creates wait states: counts from next_data_delay down to 0)
        timeleft := jptempvar39;

           --- A read cycle, don't drive ad
        IF  (NOT command(0))  = '1'  THEN
           pci_ad_oe <=  '0';
        END IF;

        IF timeout > 10 THEN
            jptempvar41 := '1';
        ELSE
            jptempvar41 := '0';
        END IF;
           ---- Deal with a timed out transaction (No devsel)
        IF  ((jptempvar41) AND (NOT devsel)) = '1' THEN
           IF frame_reg = '1' THEN
               frame_reg <=  '0';
           ELSE 
               frame_oe <=  '0';
               irdy_reg <=  '0';
               irdy_oe <=  '0';
               quit := '1';
               pci_ad_oe <=  '0';
               pci_cbe_oe <=  '0';
               idsel_oe <=  '0';
               irdy_oe <=  '0';
               req64_oe <=  '0';
               req_reg <=  '0';
               quit := '1';
             wait until rising_edge(pci_clk);
             wait until rising_edge(pci_clk);
           END IF;
        END IF;

       ---- A data phase is occuring
        IF (irdy_reg AND trdy) = '1' THEN
           IF (NOT ack64_l) = '1' THEN
               countleft := countleft - 2;
               IF trdy = '1' THEN
                  dwords_transmitted := dwords_transmitted + 2;
               END IF;
           ELSE
               countleft := countleft - 1;
               IF  trdy = '1' THEN
                  dwords_transmitted :=  dwords_transmitted + 1;
               END IF;
           END IF;

         -------- Set irdy timeout (To create irdy wait states!)
           timeleft := next_data_delay;
           irdy_reg <=  '0';
        END IF;

         ---- Compare data
        IF (NOT command(0)) = '1' THEN
           data_read(63 downto 0) :=  pci_ad(63 downto 0);
           IF (irdy AND trdy) = '1' THEN
              IF  (  NOT ack64_l )  = '1' THEN
                 compare64(std_logic_vector(unsigned(address) + to_unsigned(((dwords_transmitted-2)*4),32)), data_array(index+1) & data_array(index), pci_ad, be_array(index+1) & be_array(index), pass_fail, quiet, last_data);
              ELSE
                 compare(std_logic_vector(unsigned(address) + to_unsigned(((dwords_transmitted-1)*4),32)), data_array(index), pci_ad(31 downto 0), be_array(index), pass_fail, quiet, last_data);
              END IF;
           END IF;
        END IF;

----jptempvar42 <=  1 WHEN  ( ack64_l )  = '1'  ELSE  2;
        IF (irdy AND trdy) = '1' THEN
            IF (NOT ack64_l) = '0' THEN
               index := index + 1;
            ELSE
               index := index + 2;
            END IF;
        END IF;






-----jptempvar43 <=  '1' WHEN 
 -----( timeleft(5 downto 0) )  <  (  BASETEN1 )  ELSE '0';
          ----- REady to send/receive
        IF timeleft < 1 THEN
             ---- Its a write: put data on the bus
           IF command(0) = '1' THEN
              IF  ( m64bit )  = '1'  THEN
                 pci_ad_reg(63 downto 0) <= data_array(index + 1) &
                                 data_array(index);
                 pci_cbe_reg(7 downto 0) <= NOT (be_array(index + 1) &
                                 be_array(index)) ;
              ELSE
  -- Put zeros on upper 32 bits of data bus, with byte enable turned off
                 pci_ad_reg(63 downto 0) <= ZEROS32 & data_array(index);
                 pci_cbe_reg(7 downto 0) <= NOT ("0000" & be_array(index));
              END IF;
           END IF;


------jptempvar44 <=  '1' WHEN 
 ------( countleft )  >  (  BASETEN0 )  ELSE '0';
    ---- Assert irdy as long as we have data and we haven't been halted
    ----- (and devsel has been asserted by someone)
           IF countleft > 0 THEN
              jptempvar44 :=  '1';
           ELSE
              jptempvar44 :=  '0';
           END IF;
           IF  (((NOT stop) OR frame_reg) AND (jptempvar44)) = '1' THEN
                --- If we are just starting, check the 64/32 bit stuff
              IF ((NOT got_devsel) AND devsel) = '1' THEN
                 got_devsel :=  '1';
                 IF (ack64_l AND  m64bit) = '1' THEN
                     burst := '1';
                     countleft := 2;
                     m64bit := '0';
                 END IF;
              END IF;

              ---- Assert irdy
              irdy_reg <=  '1';