📄 cardbus_5632.vhd
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Q=>Usr_RdData(6) );
Mux_DataQ5Q : MUX4X0
Port Map ( A=>mem_RdData(5), B=>CIS_data(5), C=>cstschg_regs(5),
D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
Q=>Usr_RdData(5) );
Mux_DataQ4Q : MUX4X0
Port Map ( A=>mem_RdData(4), B=>CIS_data(4), C=>cstschg_regs(4),
D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
Q=>Usr_RdData(4) );
Mux_DataQ3Q : MUX4X0
Port Map ( A=>mem_RdData(3), B=>CIS_data(3), C=>cstschg_regs(3),
D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
Q=>Usr_RdData(3) );
Mux_DataQ2Q : MUX4X0
Port Map ( A=>mem_RdData(2), B=>CIS_data(2), C=>cstschg_regs(2),
D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
Q=>Usr_RdData(2) );
Mux_DataQ1Q : MUX4X0
Port Map ( A=>mem_RdData(1), B=>CIS_data(1), C=>cstschg_regs(1),
D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
Q=>Usr_RdData(1) );
Mux_DataQ0Q : MUX4X0
Port Map ( A=>mem_RdData(0), B=>CIS_data(0), C=>cstschg_regs(0),
D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
Q=>Usr_RdData(0) );
I228 : INPAD_25UM
Port Map ( P=>pad_CBLOCK_n, Q=>CBLOCK_n );
I234 : INPAD_25UM
Port Map ( P=>pad_PWM, Q=>PWM_in );
I235 : INPAD_25UM
Port Map ( P=>pad_BAM, Q=>BAM_in );
I236 : INPAD_25UM
Port Map ( P=>pad_wp, Q=>wp_ps );
I237 : INPAD_25UM
Port Map ( P=>pad_ready, Q=>ready_ps );
inpad_bvdQ2Q : INPAD_25UM
Port Map ( P=>pad_bvd(2), Q=>bvd_ps(2) );
inpad_bvdQ1Q : INPAD_25UM
Port Map ( P=>pad_bvd(1), Q=>bvd_ps(1) );
I239 : INPAD_25UM
Port Map ( P=>pad_gwake, Q=>gwake_ps );
I240 : INPAD_25UM
Port Map ( P=>pad_intr, Q=>intr_ps );
I233 : INPAD_25UM
Port Map ( P=>pad_clk_resume, Q=>clk_resume );
CIS_dataQ31Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(31), Q=>CIS_data(31) );
CIS_dataQ30Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(30), Q=>CIS_data(30) );
CIS_dataQ29Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(29), Q=>CIS_data(29) );
CIS_dataQ28Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(28), Q=>CIS_data(28) );
CIS_dataQ27Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(27), Q=>CIS_data(27) );
CIS_dataQ26Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(26), Q=>CIS_data(26) );
CIS_dataQ25Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(25), Q=>CIS_data(25) );
CIS_dataQ24Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(24), Q=>CIS_data(24) );
CIS_dataQ23Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(23), Q=>CIS_data(23) );
CIS_dataQ22Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(22), Q=>CIS_data(22) );
CIS_dataQ21Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(21), Q=>CIS_data(21) );
CIS_dataQ20Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(20), Q=>CIS_data(20) );
CIS_dataQ19Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(19), Q=>CIS_data(19) );
CIS_dataQ18Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(18), Q=>CIS_data(18) );
CIS_dataQ17Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(17), Q=>CIS_data(17) );
CIS_dataQ16Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(16), Q=>CIS_data(16) );
CIS_dataQ15Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(15), Q=>CIS_data(15) );
CIS_dataQ14Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(14), Q=>CIS_data(14) );
CIS_dataQ13Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(13), Q=>CIS_data(13) );
CIS_dataQ12Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(12), Q=>CIS_data(12) );
CIS_dataQ11Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(11), Q=>CIS_data(11) );
CIS_dataQ10Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(10), Q=>CIS_data(10) );
CIS_dataQ9Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(9), Q=>CIS_data(9) );
CIS_dataQ8Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(8), Q=>CIS_data(8) );
CIS_dataQ7Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(7), Q=>CIS_data(7) );
CIS_dataQ6Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(6), Q=>CIS_data(6) );
CIS_dataQ5Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(5), Q=>CIS_data(5) );
CIS_dataQ4Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(4), Q=>CIS_data(4) );
CIS_dataQ3Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(3), Q=>CIS_data(3) );
CIS_dataQ2Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(2), Q=>CIS_data(2) );
CIS_dataQ1Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(1), Q=>CIS_data(1) );
CIS_dataQ0Q : INPAD_25UM
Port Map ( P=>pad_CIS_data(0), Q=>CIS_data(0) );
I229 : BIPAD_25UM
Port Map ( A=>CCLKRUN_n_out, EN=>CCLKRUN_n_oe, P=>pad_CCLKRUN_n,
Q=>CCLKRUN_n_in );
I222 : CARDBUS_WRAPPER
Port Map ( addr_phase=>Usr_Adr_Valid, BAM_in=>BAM_in,
BAR_match=>CardBus_BAR,
bvd_ps(2 downto 1)=>bvd_ps(2 downto 1),
CBLOCK_n=>CBLOCK_n, CCLKRUN_n_in=>CCLKRUN_n_in,
clk=>PCI_clock, clk_resume=>clk_resume,
cstschg_regs_in(31 downto 0)=>Usr_Addr_WrData(31 downto 0),
framen_d1=>PCI_FRAME_D1, gwake_ps=>gwake_ps,
intr_ps=>intr_ps, PWM_in=>PWM_in, ready_ps=>ready_ps,
reset=>PCI_reset,
user_addr(9 downto 0)=>ADR(9 downto 0),
usr_read=>Usr_Read, usr_write=>Usr_Write, wp_ps=>wp_ps,
CAUDIO=>CAUDIO, CCLKRUN_n_oe=>CCLKRUN_n_oe,
CCLKRUN_n_out=>CCLKRUN_n_out, CINT_n=>CINT_n,
clk_stopped=>clk_stopped, CSTSCHG=>CSTSCHG,
cstschg_rdy=>cstschg_rdy,
cstschg_regs_oe=>RdData_MUX_sel,
cstschg_regs_out(31 downto 0)=>cstschg_regs(31 downto 0),
locked=>locked, owner_access=>owner_access );
Rdbuff : F32A32_25UM
Port Map ( din(31 downto 0)=>RdBuff_mux(31 downto 0), pop=>we_int,
push=>N_28, rclk=>local_clock, rrst=>loc_sync_reset,
wclk=>PCI_clock, wrst=>local_reset,
almostempty=>RdBuff_almost_empty, almostfull=>open,
dout(31 downto 0)=>RdBuff_out(31 downto 0),
empty=>RdBuff_empty, full=>RdBuff_full );
WrBuff : F32A32_25UM
Port Map ( din(31 downto 0)=>WrBuff_in(31 downto 0), pop=>N_26,
push=>re_dly, rclk=>PCI_clock, rrst=>local_reset,
wclk=>local_clock, wrst=>loc_sync_reset,
almostempty=>WrBuff_almost_empty,
almostfull=>WrBuff_almost_full,
dout(31 downto 0)=>Mst_WrData_FIFO(31 downto 0),
empty=>WrBuff_empty, full=>WrBuff_full );
I170 : TRIPAD_25UM
Port Map ( A=>VCC, EN=>GND, P=>INTAN_DUMMY );
I187 : GCLKBUFF_25UM
Port Map ( A=>N_20, Z=>loc_sync_reset );
I188 : GCLKBUFF_25UM
Port Map ( A=>N_19, Z=>local_reset );
I215 : GCLKBUFF_25UM
Port Map ( A=>fpga_oe, Z=>N_23 );
ladpadsQ31Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(31), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(31),
FFQ=>WrBuff_in(31), Q=>WrD(31) );
ladpadsQ30Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(30), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(30),
FFQ=>WrBuff_in(30), Q=>WrD(30) );
ladpadsQ29Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(29), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(29),
FFQ=>WrBuff_in(29), Q=>WrD(29) );
ladpadsQ28Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(28), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(28),
FFQ=>WrBuff_in(28), Q=>WrD(28) );
ladpadsQ27Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(27), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(27),
FFQ=>WrBuff_in(27), Q=>WrD(27) );
ladpadsQ26Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(26), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(26),
FFQ=>WrBuff_in(26), Q=>WrD(26) );
ladpadsQ25Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(25), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(25),
FFQ=>WrBuff_in(25), Q=>WrD(25) );
ladpadsQ24Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(24), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(24),
FFQ=>WrBuff_in(24), Q=>WrD(24) );
ladpadsQ23Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(23), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(23),
FFQ=>WrBuff_in(23), Q=>WrD(23) );
ladpadsQ22Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(22), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(22),
FFQ=>WrBuff_in(22), Q=>WrD(22) );
ladpadsQ21Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(21), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(21),
FFQ=>WrBuff_in(21), Q=>WrD(21) );
ladpadsQ20Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(20), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(20),
FFQ=>WrBuff_in(20), Q=>WrD(20) );
ladpadsQ19Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(19), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(19),
FFQ=>WrBuff_in(19), Q=>WrD(19) );
ladpadsQ18Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(18), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(18),
FFQ=>WrBuff_in(18), Q=>WrD(18) );
ladpadsQ17Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(17), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(17),
FFQ=>WrBuff_in(17), Q=>WrD(17) );
ladpadsQ16Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(16), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(16),
FFQ=>WrBuff_in(16), Q=>WrD(16) );
ladpadsQ15Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(15), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(15),
FFQ=>WrBuff_in(15), Q=>WrD(15) );
ladpadsQ14Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(14), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(14),
FFQ=>WrBuff_in(14), Q=>WrD(14) );
ladpadsQ13Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(13), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(13),
FFQ=>WrBuff_in(13), Q=>WrD(13) );
ladpadsQ12Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(12), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(12),
FFQ=>WrBuff_in(12), Q=>WrD(12) );
ladpadsQ11Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(11), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(11),
FFQ=>WrBuff_in(11), Q=>WrD(11) );
ladpadsQ10Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(10), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(10),
FFQ=>WrBuff_in(10), Q=>WrD(10) );
ladpadsQ9Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(9), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(9),
FFQ=>WrBuff_in(9), Q=>WrD(9) );
ladpadsQ8Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(8), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(8),
FFQ=>WrBuff_in(8), Q=>WrD(8) );
ladpadsQ7Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(7), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(7),
FFQ=>WrBuff_in(7), Q=>WrD(7) );
ladpadsQ6Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(6), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(6),
FFQ=>WrBuff_in(6), Q=>WrD(6) );
ladpadsQ5Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(5), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(5),
FFQ=>WrBuff_in(5), Q=>WrD(5) );
ladpadsQ4Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(4), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(4),
FFQ=>WrBuff_in(4), Q=>WrD(4) );
ladpadsQ3Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(3), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(3),
FFQ=>WrBuff_in(3), Q=>WrD(3) );
ladpadsQ2Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(2), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(2),
FFQ=>WrBuff_in(2), Q=>WrD(2) );
ladpadsQ1Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(1), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(1),
FFQ=>WrBuff_in(1), Q=>WrD(1) );
ladpadsQ0Q : BIPADIFF_25UM
Port Map ( A2=>RdBuff_out(0), EN=>N_23, FFCLK=>local_clock,
FFCLR=>loc_sync_reset, FFEN=>N_25, P=>lad(0),
FFQ=>WrBuff_in(0), Q=>WrD(0) );
I189 : CKPAD_25UM
Port Map ( P=>lclk, Q=>local_clock );
I241 : OUTPAD_25UM
Port Map ( A=>owner_access, P=>pad_owner_access_DUMMY );
I242 : OUTPAD_25UM
Port Map ( A=>locked, P=>pad_locked_DUMMY );
I243 : OUTPAD_25UM
Port Map ( A=>clk_stopped, P=>pad_clk_stopped_DUMMY );
I230 : OUTPAD_25UM
Port Map ( A=>CAUDIO, P=>pad_CAUDIO_DUMMY );
I231 : OUTPAD_25UM
Port Map ( A=>CSTSCHG, P=>pad_CSTSCHG_DUMMY );
I232 : OUTPAD_25UM
Port Map ( A=>CINT_n, P=>pad_CINT_n_DUMMY );
CIS_ADRQ9Q : OUTPAD_25UM
Port Map ( A=>ADR(9), P=>pad_CIS_ADR_DUMMY(9) );
CIS_ADRQ8Q : OUTPAD_25UM
Port Map ( A=>ADR(8), P=>pad_CIS_ADR_DUMMY(8) );
CIS_ADRQ7Q : OUTPAD_25UM
Port Map ( A=>ADR(7), P=>pad_CIS_ADR_DUMMY(7) );
CIS_ADRQ6Q : OUTPAD_25UM
Port Map ( A=>ADR(6), P=>pad_CIS_ADR_DUMMY(6) );
CIS_ADRQ5Q : OUTPAD_25UM
Port Map ( A=>ADR(5), P=>pad_CIS_ADR_DUMMY(5) );
CIS_ADRQ4Q : OUTPAD_25UM
Port Map ( A=>ADR(4), P=>pad_CIS_ADR_DUMMY(4) );
CIS_ADRQ3Q : OUTPAD_25UM
Port Map ( A=>ADR(3), P=>pad_CIS_ADR_DUMMY(3) );
CIS_ADRQ2Q : OUTPAD_25UM
Port Map ( A=>ADR(2), P=>pad_CIS_ADR_DUMMY(2) );
I217 : OUTPAD_25UM
Port Map ( A=>N_18, P=>mrs_DUMMY );
ledpadsQ7Q : OUTPAD_25UM
Port Map ( A=>mxledoi(7), P=>led_DUMMY(7) );
ledpadsQ6Q : OUTPAD_25UM
Port Map ( A=>mxledoi(6), P=>led_DUMMY(6) );
ledpadsQ5Q : OUTPAD_25UM
Port Map ( A=>mxle⌨️ 快捷键说明
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