cardbus_5632.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

   component OR2I0
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component MUX2X0
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   S : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component DMAREGRD
      Port (     adr : In    STD_LOGIC_VECTOR  (9 downto 2);
                 CBE : In    STD_LOGIC_VECTOR  (3 downto 0);
                 clk : In    STD_LOGIC;
                 clr : In    STD_LOGIC;
             DMARdEn : In    STD_LOGIC;
             DMAWrEn : In    STD_LOGIC;
             IncrAddr : In    STD_LOGIC;
             LoadAddr : In    STD_LOGIC;
             PCI_data : In    STD_LOGIC_VECTOR  (31 downto 0);
              PCI_Wr : In    STD_LOGIC;
              clkspd : Out   STD_LOGIC_VECTOR  (2 downto 0);
             dataout : Out   STD_LOGIC_VECTOR  (31 downto 0);
                 led : Out   STD_LOGIC_VECTOR  (7 downto 0);
             ledcntrl : Out   STD_LOGIC;
             Usr_Rdy : Out   STD_LOGIC;
             Usr_Stop : Out   STD_LOGIC );
   end component;

   component FIFOCONT
      Port (     clk : In    STD_LOGIC;
                 clr : In    STD_LOGIC;
             idt_fifo_ae_n : In    STD_LOGIC;
             idt_fifo_af_n : In    STD_LOGIC;
             idt_fifo_empty : In    STD_LOGIC;
             idt_fifo_full : In    STD_LOGIC;
             rbuff_ae : In    STD_LOGIC;
             rbuff_empty : In    STD_LOGIC;
             wbuff_af : In    STD_LOGIC;
             wbuff_full : In    STD_LOGIC;
             fpga_oe : Out   STD_LOGIC;
             idt_fifo_oe_n : Out   STD_LOGIC;
                 ldn : Out   STD_LOGIC;
                  re : Out   STD_LOGIC;
              re_dly : Out   STD_LOGIC;
                  we : Out   STD_LOGIC;
              we_int : Out   STD_LOGIC );
   end component;

   component DFFP
      Port (     CLK : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                 PRE : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component INITFLGS
      Port (     clk : In    STD_LOGIC;
                 clr : In    STD_LOGIC;
              datain : In    STD_LOGIC_VECTOR  (31 downto 0);
              pushin : In    STD_LOGIC;
             dataout : Out   STD_LOGIC_VECTOR  (31 downto 0);
                push : Out   STD_LOGIC );
   end component;

   component INV
      Port (       A : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component DMACNTRL
      Port ( BusMstEn : In    STD_LOGIC;
             IncrAddr : In    STD_LOGIC;
              LastWr : In    STD_LOGIC;
             Mst_BE_FIFO : In    STD_LOGIC_VECTOR  (3 downto 0);
             Mst_RdBurst_Done : In    STD_LOGIC;
             Mst_RdData_Valid : In    STD_LOGIC;
             Mst_Tabort_Det : In    STD_LOGIC;
             Mst_TTO_Det : In    STD_LOGIC;
             Mst_WrBurst_Done : In    STD_LOGIC;
             Mst_WrData_Rdy : In    STD_LOGIC;
             Mst_Xfer_D1 : In    STD_LOGIC;
             PCI_clk : In    STD_LOGIC;
             PCI_reset : In    STD_LOGIC;
               RdRdy : In    STD_LOGIC;
              Usr_Ad : In    STD_LOGIC_VECTOR  (9 downto 2);
             Usr_CBE : In    STD_LOGIC_VECTOR  (3 downto 0);
             Usr_RdDataIn : In    STD_LOGIC_VECTOR  (31 downto 0);
             Usr_WrData : In    STD_LOGIC_VECTOR  (31 downto 0);
             Usr_Write : In    STD_LOGIC;
               WrRdy : In    STD_LOGIC;
              BEfifo : Out   STD_LOGIC;
             DMARdEn : Out   STD_LOGIC;
             DMAWrEn : Out   STD_LOGIC;
             LocalEn : Out   STD_LOGIC;
              Mst_BE : Out   STD_LOGIC_VECTOR  (3 downto 0);
             Mst_BE_Sel : Out   STD_LOGIC;
             Mst_Burst_Req : Out   STD_LOGIC;
             Mst_Data_Sel : Out   STD_LOGIC;
             Mst_LatCntEn : Out   STD_LOGIC;
             Mst_One_Read : Out   STD_LOGIC;
             Mst_Rd_Term_Sel : Out   STD_LOGIC;
             Mst_RdAd : Out   STD_LOGIC_VECTOR  (31 downto 0);
             Mst_Two_Reads : Out   STD_LOGIC;
             Mst_WrAd : Out   STD_LOGIC_VECTOR  (31 downto 0);
             Mst_WrData_Valid : Out   STD_LOGIC;
             MstRdAd_Sel : Out   STD_LOGIC;
             MstWrAd_Sel : Out   STD_LOGIC;
             PCI_Cmd : Out   STD_LOGIC_VECTOR  (3 downto 0);
             Usr_RdData : Out   STD_LOGIC_VECTOR  (31 downto 0);
              WD_Reg : Out   STD_LOGIC_VECTOR  (31 downto 0) );
   end component;

begin


   ren <= ren_DUMMY;
   oe <= oe_DUMMY;
   wen <= wen_DUMMY;
   ld <= ld_DUMMY;
   led(7 downto 0) <= led_DUMMY(7 downto 0);
   mrs <= mrs_DUMMY;
   pad_CIS_ADR(9 downto 2) <= pad_CIS_ADR_DUMMY(9 downto 2);
   REQN <= REQN_DUMMY;
   SERRN <= SERRN_DUMMY;
   INTAN <= INTAN_DUMMY;
   pad_owner_access <= pad_owner_access_DUMMY;
   pad_locked <= pad_locked_DUMMY;
   pad_clk_stopped <= pad_clk_stopped_DUMMY;
   pad_CAUDIO <= pad_CAUDIO_DUMMY;
   pad_CSTSCHG <= pad_CSTSCHG_DUMMY;
   pad_CINT_n <= pad_CINT_n_DUMMY;
   I251 : F128X4_25UM
      Port Map ( clk=>PCI_clock,
                 din(3 downto 0)=>Usr_Addr_WrData(3 downto 0),
                 pop=>BEFIFO_pop, push=>BEfifo, rst=>PCI_reset,
                 dout(3 downto 0)=>Mst_BE_FIFO(3 downto 0),
                 emptyn=>BEFIFO_emptyn, fulln=>BEFIFO_fulln );
   I250 : CIS_DECODE
      Port Map ( addr_phase=>Usr_Adr_Valid, BAR_match=>CardBus_BAR,
                 clk=>PCI_clock, last_cycle=>Usr_Last_Cycle_D1,
                 reset=>PCI_reset,
                 user_addr(9 downto 4)=>Usr_Addr_WrData(9 downto 4),
                 CIS_Hit=>CIS_sel );
   I249 : CFGTADDR_CARDBUS
      Port Map ( CBE(3 downto 0)=>Usr_CBE(3 downto 0),
                 Cfg_Write=>Cfg_Write, IncrAddr=>Usr_Adr_Inc,
                 LoadAddr=>Usr_Adr_Valid, MstPERR_Det=>Cfg_MstPERR_Det,
                 MstSC=>MstSC, PCI_clock=>PCI_clock,
                 PCI_reset=>PCI_reset, PERR_Det=>Cfg_PERR_Det,
                 SERR_Sig=>Cfg_SERR_Sig, Tabort_Det=>Mst_Tabort_Det,
                 TTO_Det=>Mst_TTO_Det,
                 WrData(31 downto 0)=>Usr_Addr_WrData(31 downto 0),
                 Addr_Hit=>Usr_Select, BAR0_Hit=>open,
                 BAR5_Hit=>CardBus_BAR,
                 CacheLineSizeReg(7 downto 2)=>Cfg_CacheLineSize(7 downto 2),
                 CfgData(31 downto 0)=>Cfg_RdData(31 downto 0),
                 CmdReg(15 downto 0)=>Cfg_CmdReg(15 downto 0),
                 LatTimerReg(7 downto 0)=>Cfg_LatCnt(7 downto 0),
                 Usr_RdCmd=>Usr_RdDecode, Usr_Stop=>Cfg_Stop,
                 Usr_WrCmd=>Usr_WrDecode,
                 UsrAddr(9 downto 0)=>ADR(9 downto 0) );
   I248 : PCI32_25UM
      Port Map ( Cfg_CacheLineSize(7 downto 2)=>Cfg_CacheLineSize(7 downto 2),
                 Cfg_CmdReg3=>Cfg_CmdReg(3), Cfg_CmdReg4=>Cfg_CmdReg(4),
                 Cfg_CmdReg6=>Cfg_CmdReg(6), Cfg_CmdReg8=>Cfg_CmdReg(8),
                 Cfg_LatCnt(7 downto 0)=>Cfg_LatCnt(7 downto 0),
                 Cfg_RdData(31 downto 0)=>Cfg_RdData(31 downto 0),
                 CLK=>CLK, Flush_FIFO=>GND, GNTN=>GNTN, IDSEL=>IDSEL,
                 Mst_BE(3 downto 0)=>Mst_BE(3 downto 0),
                 Mst_BE_Sel=>Mst_BE_Sel, Mst_Burst_Req=>Mst_Burst_Req,
                 Mst_LatCntEn=>Mst_LatCntEn, Mst_One_Read=>Mst_One_Read,
                 Mst_Rd_Term_Sel=>Mst_Rd_Term_Sel,
                 Mst_RdAd(31 downto 0)=>Mst_RdAd(31 downto 0),
                 Mst_Two_Reads=>Mst_Two_Reads,
                 Mst_WrAd(31 downto 0)=>Mst_WrAd(31 downto 0),
                 Mst_WrData(31 downto 0)=>Mst_WrData(31 downto 0),
                 Mst_WrData_Valid=>Mst_WrData_Valid,
                 PCI_Cmd(3 downto 0)=>PCI_Cmd(3 downto 0), RSTN=>RSTN,
                 Usr_Abort=>GND, Usr_MstRdAd_Sel=>Usr_MstRdAd_Sel,
                 Usr_MstWrAd_Sel=>Usr_MstWrAd_Sel,
                 Usr_RdData(31 downto 0)=>Usr_RdData(31 downto 0),
                 Usr_RdDecode=>Usr_RdDecode, Usr_Rdy=>Usr_Rdy,
                 Usr_Select=>Usr_Select, Usr_Stop=>Usr_Stop,
                 Usr_WrDecode=>Usr_WrDecode,
                 AD(31 downto 0)=>AD(31 downto 0),
                 CBEN(3 downto 0)=>CBEN(3 downto 0), DEVSELN=>DEVSELN,
                 FRAMEN=>FRAMEN, IRDYN=>IRDYN, PAR=>PAR, PERRN=>PERRN,
                 STOPN=>STOPN, TRDYN=>TRDYN,
                 Cfg_MstPERR_Det=>Cfg_MstPERR_Det,
                 Cfg_PERR_Det=>Cfg_PERR_Det, Cfg_Read=>open,
                 Cfg_SERR_Sig=>Cfg_SERR_Sig, Cfg_Write=>Cfg_Write,
                 Mst_IRDYN=>open, Mst_Last_Cycle=>open,
                 Mst_RdBurst_Done=>Mst_RdBurst_Done,
                 Mst_RdData_Valid=>Mst_RdData_Valid, Mst_REQN=>open,
                 Mst_Tabort_Det=>Mst_Tabort_Det,
                 Mst_TTO_Det=>Mst_TTO_Det,
                 Mst_WrBurst_Done=>Mst_WrBurst_Done,
                 Mst_WrData_Rdy=>Mst_WrData_Rdy,
                 Mst_Xfer_D1=>Mst_Xfer_D1, PCI_clock=>PCI_clock,
                 PCI_DEVSELN_D1=>open, PCI_FRAMEN_D1=>PCI_FRAME_D1,
                 PCI_GNTN_D1=>open, PCI_IDSEL_D1=>open,
                 PCI_IRDYN_D1=>open, PCI_reset=>PCI_reset,
                 PCI_STOPN_D1=>open, PCI_TRDYN_D1=>open,
                 REQN=>REQN_DUMMY, SERRN=>SERRN_DUMMY,
                 Usr_Addr_WrData(31 downto 0)=>Usr_Addr_WrData(31 downto 0),
                 Usr_Adr_Inc=>Usr_Adr_Inc, Usr_Adr_Valid=>Usr_Adr_Valid,
                 Usr_CBE(3 downto 0)=>Usr_CBE(3 downto 0),
                 Usr_DEVSEL=>open, Usr_Last_Cycle_D1=>Usr_Last_Cycle_D1,
                 Usr_Read=>Usr_Read, Usr_STOPO=>open, Usr_TRDY=>open,
                 Usr_Write=>Usr_Write );
   Rdy_Mux : MUX4X0
      Port Map ( A=>Mem_Rdy, B=>CIS_sel, C=>cstschg_rdy, D=>GND,
                 S0=>CIS_sel, S1=>RdData_MUX_sel, Q=>Usr_Rdy );
   Mux_DataQ31Q : MUX4X0
      Port Map ( A=>mem_RdData(31), B=>CIS_data(31), C=>cstschg_regs(31),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(31) );
   Mux_DataQ30Q : MUX4X0
      Port Map ( A=>mem_RdData(30), B=>CIS_data(30), C=>cstschg_regs(30),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(30) );
   Mux_DataQ29Q : MUX4X0
      Port Map ( A=>mem_RdData(29), B=>CIS_data(29), C=>cstschg_regs(29),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(29) );
   Mux_DataQ28Q : MUX4X0
      Port Map ( A=>mem_RdData(28), B=>CIS_data(28), C=>cstschg_regs(28),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(28) );
   Mux_DataQ27Q : MUX4X0
      Port Map ( A=>mem_RdData(27), B=>CIS_data(27), C=>cstschg_regs(27),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(27) );
   Mux_DataQ26Q : MUX4X0
      Port Map ( A=>mem_RdData(26), B=>CIS_data(26), C=>cstschg_regs(26),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(26) );
   Mux_DataQ25Q : MUX4X0
      Port Map ( A=>mem_RdData(25), B=>CIS_data(25), C=>cstschg_regs(25),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(25) );
   Mux_DataQ24Q : MUX4X0
      Port Map ( A=>mem_RdData(24), B=>CIS_data(24), C=>cstschg_regs(24),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(24) );
   Mux_DataQ23Q : MUX4X0
      Port Map ( A=>mem_RdData(23), B=>CIS_data(23), C=>cstschg_regs(23),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(23) );
   Mux_DataQ22Q : MUX4X0
      Port Map ( A=>mem_RdData(22), B=>CIS_data(22), C=>cstschg_regs(22),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(22) );
   Mux_DataQ21Q : MUX4X0
      Port Map ( A=>mem_RdData(21), B=>CIS_data(21), C=>cstschg_regs(21),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(21) );
   Mux_DataQ20Q : MUX4X0
      Port Map ( A=>mem_RdData(20), B=>CIS_data(20), C=>cstschg_regs(20),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(20) );
   Mux_DataQ19Q : MUX4X0
      Port Map ( A=>mem_RdData(19), B=>CIS_data(19), C=>cstschg_regs(19),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(19) );
   Mux_DataQ18Q : MUX4X0
      Port Map ( A=>mem_RdData(18), B=>CIS_data(18), C=>cstschg_regs(18),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(18) );
   Mux_DataQ17Q : MUX4X0
      Port Map ( A=>mem_RdData(17), B=>CIS_data(17), C=>cstschg_regs(17),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(17) );
   Mux_DataQ16Q : MUX4X0
      Port Map ( A=>mem_RdData(16), B=>CIS_data(16), C=>cstschg_regs(16),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(16) );
   Mux_DataQ15Q : MUX4X0
      Port Map ( A=>mem_RdData(15), B=>CIS_data(15), C=>cstschg_regs(15),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(15) );
   Mux_DataQ14Q : MUX4X0
      Port Map ( A=>mem_RdData(14), B=>CIS_data(14), C=>cstschg_regs(14),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(14) );
   Mux_DataQ13Q : MUX4X0
      Port Map ( A=>mem_RdData(13), B=>CIS_data(13), C=>cstschg_regs(13),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(13) );
   Mux_DataQ12Q : MUX4X0
      Port Map ( A=>mem_RdData(12), B=>CIS_data(12), C=>cstschg_regs(12),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(12) );
   Mux_DataQ11Q : MUX4X0
      Port Map ( A=>mem_RdData(11), B=>CIS_data(11), C=>cstschg_regs(11),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(11) );
   Mux_DataQ10Q : MUX4X0
      Port Map ( A=>mem_RdData(10), B=>CIS_data(10), C=>cstschg_regs(10),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(10) );
   Mux_DataQ9Q : MUX4X0
      Port Map ( A=>mem_RdData(9), B=>CIS_data(9), C=>cstschg_regs(9),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(9) );
   Mux_DataQ8Q : MUX4X0
      Port Map ( A=>mem_RdData(8), B=>CIS_data(8), C=>cstschg_regs(8),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(8) );
   Mux_DataQ7Q : MUX4X0
      Port Map ( A=>mem_RdData(7), B=>CIS_data(7), C=>cstschg_regs(7),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,
                 Q=>Usr_RdData(7) );
   Mux_DataQ6Q : MUX4X0
      Port Map ( A=>mem_RdData(6), B=>CIS_data(6), C=>cstschg_regs(6),
                 D=>gnd_bit, S0=>CIS_sel, S1=>RdData_MUX_sel,