cardbus_5632.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

   signal Usr_Select : STD_LOGIC;
   signal Usr_RdDecode : STD_LOGIC;
   signal Usr_WrDecode : STD_LOGIC;
   signal Mst_WrData_Rdy : STD_LOGIC;
   signal PCI_reset : STD_LOGIC;
   signal Mst_BE_Sel : STD_LOGIC;
   signal Mst_Burst_Req : STD_LOGIC;
   signal BEFIFO_pop : STD_LOGIC;
   signal BEFIFO_emptyn : STD_LOGIC;
   signal PCI_clock : STD_LOGIC;
   signal    MstSC : STD_LOGIC;
   signal ren_DUMMY : STD_LOGIC;
   signal oe_DUMMY : STD_LOGIC;
   signal wen_DUMMY : STD_LOGIC;
   signal ld_DUMMY : STD_LOGIC;
   signal led_DUMMY : STD_LOGIC_VECTOR  (7 downto 0);
   signal mrs_DUMMY : STD_LOGIC;
   signal pad_CIS_ADR_DUMMY : STD_LOGIC_VECTOR  (9 downto 2);
   signal REQN_DUMMY : STD_LOGIC;
   signal SERRN_DUMMY : STD_LOGIC;
   signal INTAN_DUMMY : STD_LOGIC;
   signal pad_owner_access_DUMMY : STD_LOGIC;
   signal pad_locked_DUMMY : STD_LOGIC;
   signal pad_clk_stopped_DUMMY : STD_LOGIC;
   signal pad_CAUDIO_DUMMY : STD_LOGIC;
   signal pad_CSTSCHG_DUMMY : STD_LOGIC;
   signal pad_CINT_n_DUMMY : STD_LOGIC;

   component F128X4_25UM
      Port (     clk : In    STD_LOGIC;
                 din : In    STD_LOGIC_VECTOR  (3 downto 0);
                 pop : In    STD_LOGIC;
                push : In    STD_LOGIC;
                 rst : In    STD_LOGIC;
                dout : Out   STD_LOGIC_VECTOR  (3 downto 0);
              emptyn : Out   STD_LOGIC;
               fulln : Out   STD_LOGIC );
   end component;

   component CIS_DECODE
      Port ( addr_phase : In    STD_LOGIC;
             BAR_match : In    STD_LOGIC;
                 clk : In    STD_LOGIC;
             last_cycle : In    STD_LOGIC;
               reset : In    STD_LOGIC;
             user_addr : In    STD_LOGIC_VECTOR  (9 downto 4);
             CIS_Hit : Out   STD_LOGIC );
   end component;

   component CFGTADDR_CARDBUS
      Port (     CBE : In    STD_LOGIC_VECTOR  (3 downto 0);
             Cfg_Write : In    STD_LOGIC;
             IncrAddr : In    STD_LOGIC;
             LoadAddr : In    STD_LOGIC;
             MstPERR_Det : In    STD_LOGIC;
               MstSC : In    STD_LOGIC;
             PCI_clock : In    STD_LOGIC;
             PCI_reset : In    STD_LOGIC;
             PERR_Det : In    STD_LOGIC;
             SERR_Sig : In    STD_LOGIC;
             Tabort_Det : In    STD_LOGIC;
             TTO_Det : In    STD_LOGIC;
              WrData : In    STD_LOGIC_VECTOR  (31 downto 0);
             Addr_Hit : Out   STD_LOGIC;
             BAR0_Hit : Out   STD_LOGIC;
             BAR5_Hit : Out   STD_LOGIC;
             CacheLineSizeReg : Out   STD_LOGIC_VECTOR  (7 downto 2);
             CfgData : Out   STD_LOGIC_VECTOR  (31 downto 0);
              CmdReg : Out   STD_LOGIC_VECTOR  (15 downto 0);
             LatTimerReg : Out   STD_LOGIC_VECTOR  (7 downto 0);
             Usr_RdCmd : Out   STD_LOGIC;
             Usr_Stop : Out   STD_LOGIC;
             Usr_WrCmd : Out   STD_LOGIC;
             UsrAddr : Out   STD_LOGIC_VECTOR  (9 downto 0) );
   end component;

   component PCI32_25UM
      Port ( Cfg_CacheLineSize : In    STD_LOGIC_VECTOR  (7 downto 2);
             Cfg_CmdReg3 : In    STD_LOGIC;
             Cfg_CmdReg4 : In    STD_LOGIC;
             Cfg_CmdReg6 : In    STD_LOGIC;
             Cfg_CmdReg8 : In    STD_LOGIC;
             Cfg_LatCnt : In    STD_LOGIC_VECTOR  (7 downto 0);
             Cfg_RdData : In    STD_LOGIC_VECTOR  (31 downto 0);
                 CLK : In    STD_LOGIC;
             Flush_FIFO : In    STD_LOGIC;
                GNTN : In    STD_LOGIC;
               IDSEL : In    STD_LOGIC;
              Mst_BE : In    STD_LOGIC_VECTOR  (3 downto 0);
             Mst_BE_Sel : In    STD_LOGIC;
             Mst_Burst_Req : In    STD_LOGIC;
             Mst_LatCntEn : In    STD_LOGIC;
             Mst_One_Read : In    STD_LOGIC;
             Mst_Rd_Term_Sel : In    STD_LOGIC;
             Mst_RdAd : In    STD_LOGIC_VECTOR  (31 downto 0);
             Mst_Two_Reads : In    STD_LOGIC;
             Mst_WrAd : In    STD_LOGIC_VECTOR  (31 downto 0);
             Mst_WrData : In    STD_LOGIC_VECTOR  (31 downto 0);
             Mst_WrData_Valid : In    STD_LOGIC;
             PCI_Cmd : In    STD_LOGIC_VECTOR  (3 downto 0);
                RSTN : In    STD_LOGIC;
             Usr_Abort : In    STD_LOGIC;
             Usr_MstRdAd_Sel : In    STD_LOGIC;
             Usr_MstWrAd_Sel : In    STD_LOGIC;
             Usr_RdData : In    STD_LOGIC_VECTOR  (31 downto 0);
             Usr_RdDecode : In    STD_LOGIC;
             Usr_Rdy : In    STD_LOGIC;
             Usr_Select : In    STD_LOGIC;
             Usr_Stop : In    STD_LOGIC;
             Usr_WrDecode : In    STD_LOGIC;
                  AD : InOut STD_LOGIC_VECTOR  (31 downto 0);
                CBEN : InOut STD_LOGIC_VECTOR  (3 downto 0);
             DEVSELN : InOut STD_LOGIC;
              FRAMEN : InOut STD_LOGIC;
               IRDYN : InOut STD_LOGIC;
                 PAR : InOut STD_LOGIC;
               PERRN : InOut STD_LOGIC;
               STOPN : InOut STD_LOGIC;
               TRDYN : InOut STD_LOGIC;
             Cfg_MstPERR_Det : Out   STD_LOGIC;
             Cfg_PERR_Det : Out   STD_LOGIC;
             Cfg_Read : Out   STD_LOGIC;
             Cfg_SERR_Sig : Out   STD_LOGIC;
             Cfg_Write : Out   STD_LOGIC;
             Mst_IRDYN : Out   STD_LOGIC;
             Mst_Last_Cycle : Out   STD_LOGIC;
             Mst_RdBurst_Done : Out   STD_LOGIC;
             Mst_RdData_Valid : Out   STD_LOGIC;
             Mst_REQN : Out   STD_LOGIC;
             Mst_Tabort_Det : Out   STD_LOGIC;
             Mst_TTO_Det : Out   STD_LOGIC;
             Mst_WrBurst_Done : Out   STD_LOGIC;
             Mst_WrData_Rdy : Out   STD_LOGIC;
             Mst_Xfer_D1 : Out   STD_LOGIC;
             PCI_clock : Out   STD_LOGIC;
             PCI_DEVSELN_D1 : Out   STD_LOGIC;
             PCI_FRAMEN_D1 : Out   STD_LOGIC;
             PCI_GNTN_D1 : Out   STD_LOGIC;
             PCI_IDSEL_D1 : Out   STD_LOGIC;
             PCI_IRDYN_D1 : Out   STD_LOGIC;
             PCI_reset : Out   STD_LOGIC;
             PCI_STOPN_D1 : Out   STD_LOGIC;
             PCI_TRDYN_D1 : Out   STD_LOGIC;
                REQN : Out   STD_LOGIC;
               SERRN : Out   STD_LOGIC;
             Usr_Addr_WrData : Out   STD_LOGIC_VECTOR  (31 downto 0);
             Usr_Adr_Inc : Out   STD_LOGIC;
             Usr_Adr_Valid : Out   STD_LOGIC;
             Usr_CBE : Out   STD_LOGIC_VECTOR  (3 downto 0);
             Usr_DEVSEL : Out   STD_LOGIC;
             Usr_Last_Cycle_D1 : Out   STD_LOGIC;
             Usr_Read : Out   STD_LOGIC;
             Usr_STOPO : Out   STD_LOGIC;
             Usr_TRDY : Out   STD_LOGIC;
             Usr_Write : Out   STD_LOGIC );
   end component;

   component MUX4X0
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   C : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                  S0 : In    STD_LOGIC;
                  S1 : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component INPAD_25UM
      Port (       P : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component BIPAD_25UM
      Port (       A : In    STD_LOGIC;
                  EN : In    STD_LOGIC;
                   P : InOut STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component CARDBUS_WRAPPER
      Port ( addr_phase : In    STD_LOGIC;
              BAM_in : In    STD_LOGIC;
             BAR_match : In    STD_LOGIC;
              bvd_ps : In    STD_LOGIC_VECTOR  (2 downto 1);
             CBLOCK_n : In    STD_LOGIC;
             CCLKRUN_n_in : In    STD_LOGIC;
                 clk : In    STD_LOGIC;
             clk_resume : In    STD_LOGIC;
             cstschg_regs_in : In    STD_LOGIC_VECTOR  (31 downto 0);
             framen_d1 : In    STD_LOGIC;
             gwake_ps : In    STD_LOGIC;
             intr_ps : In    STD_LOGIC;
              PWM_in : In    STD_LOGIC;
             ready_ps : In    STD_LOGIC;
               reset : In    STD_LOGIC;
             user_addr : In    STD_LOGIC_VECTOR  (9 downto 0);
             usr_read : In    STD_LOGIC;
             usr_write : In    STD_LOGIC;
               wp_ps : In    STD_LOGIC;
              CAUDIO : Out   STD_LOGIC;
             CCLKRUN_n_oe : Out   STD_LOGIC;
             CCLKRUN_n_out : Out   STD_LOGIC;
              CINT_n : Out   STD_LOGIC;
             clk_stopped : Out   STD_LOGIC;
             CSTSCHG : Out   STD_LOGIC;
             cstschg_rdy : Out   STD_LOGIC;
             cstschg_regs_oe : Out   STD_LOGIC;
             cstschg_regs_out : Out   STD_LOGIC_VECTOR  (31 downto 0);
              locked : Out   STD_LOGIC;
             owner_access : Out   STD_LOGIC );
   end component;

   component F32A32_25UM
      Port (     din : In    STD_LOGIC_VECTOR  (31 downto 0);
                 pop : In    STD_LOGIC;
                push : In    STD_LOGIC;
                rclk : In    STD_LOGIC;
                rrst : In    STD_LOGIC;
                wclk : In    STD_LOGIC;
                wrst : In    STD_LOGIC;
             almostempty : Out   STD_LOGIC;
             almostfull : Out   STD_LOGIC;
                dout : Out   STD_LOGIC_VECTOR  (31 downto 0);
               empty : Out   STD_LOGIC;
                full : Out   STD_LOGIC );
   end component;

   component TRIPAD_25UM
      Port (       A : In    STD_LOGIC;
                  EN : In    STD_LOGIC;
                   P : Out   STD_LOGIC );
   end component;

   component GCLKBUFF_25UM
      Port (       A : In    STD_LOGIC;
                   Z : Out   STD_LOGIC );
   end component;

   component BIPADIFF_25UM
      Port (      A2 : In    STD_LOGIC;
                  EN : In    STD_LOGIC;
               FFCLK : In    STD_LOGIC;
               FFCLR : In    STD_LOGIC;
                FFEN : In    STD_LOGIC;
                   P : InOut STD_LOGIC;
                 FFQ : Out   STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component CKPAD_25UM
      Port (       P : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component OUTPAD_25UM
      Port (       A : In    STD_LOGIC;
                   P : Out   STD_LOGIC );
   end component;

   component INPADFF_25UM
      Port (   FFCLK : In    STD_LOGIC;
               FFCLR : In    STD_LOGIC;
                FFEN : In    STD_LOGIC;
                   P : In    STD_LOGIC;
                 FFQ : Out   STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND3I2
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   C : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component DFF
      Port (     CLK : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND4I3
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   C : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component DFFE
      Port (     CLK : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                  EN : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND3I1
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   C : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component OR3I0
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   C : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND2I1
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND2I0
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;