cardbus_5632.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

             almost_on : Out   STD_LOGIC;
             flag_on : Out   STD_LOGIC );
   end component;

   component DFFPA
      Port (     CLK : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                   S : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component GCNTE5_0
      Port (     CLK : In    STD_LOGIC;
                 CLR : In    STD_LOGIC;
                  EN : In    STD_LOGIC;
                   Q : Out   STD_LOGIC_VECTOR  (4 downto 0) );
   end component;

   component RGEC5_1R
      Port (     CLK : In    STD_LOGIC;
                 CLR : In    STD_LOGIC;
                   D : In    STD_LOGIC_VECTOR  (4 downto 0);
                  EN : In    STD_LOGIC;
                   Q : Out   STD_LOGIC_VECTOR  (4 downto 0) );
   end component;

   component RGEC5_2
      Port (     CLK : In    STD_LOGIC;
                 CLR : In    STD_LOGIC;
                   D : In    STD_LOGIC_VECTOR  (4 downto 0);
                  EN : In    STD_LOGIC;
                   Q : Out   STD_LOGIC_VECTOR  (4 downto 0) );
   end component;

   component GCNTE5_2
      Port (     CLK : In    STD_LOGIC;
                 CLR : In    STD_LOGIC;
                  EN : In    STD_LOGIC;
                   Q : Out   STD_LOGIC_VECTOR  (4 downto 0) );
   end component;

   component GCNTE5_3
      Port (     CLK : In    STD_LOGIC;
                 CLR : In    STD_LOGIC;
                  EN : In    STD_LOGIC;
                   Q : Out   STD_LOGIC_VECTOR  (4 downto 0) );
   end component;

   component OR2I0
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND2I1
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component ECOMP5
      Port (       A : In    STD_LOGIC_VECTOR  (4 downto 0);
                   B : In    STD_LOGIC_VECTOR  (4 downto 0);
                  EQ : Out   STD_LOGIC );
   end component;

begin


   almostempty <= almostempty_DUMMY;
   almostfull <= almostfull_DUMMY;
   dout(31 downto 0) <= dout_DUMMY(31 downto 0);
   empty <= empty_DUMMY;
   full <= full_DUMMY;
   I137 : R128X32_25UM
      Port Map ( ra(6)=>gnd, ra(5)=>gnd,
                 ra(4 downto 0)=>Raddr1(4 downto 0), rclk=>rclk,
                 re=>N_11, wa(6)=>gnd, wa(5)=>gnd,
                 wa(4 downto 0)=>Waddr0(4 downto 0), wclk=>wclk,
                 wd(31 downto 0)=>din(31 downto 0), we=>N_4,
                 rd(31 downto 0)=>dout_DUMMY(31 downto 0) );
   I135 : AFIFOFLG
      Port Map ( clk=>wclk, holdoff=>gnd, one=>minus1, reset=>wrst,
                 rw=>push, set=>gnd, two=>minus2, zero=>zero,
                 almost_on=>almostfull_DUMMY, flag_on=>full_DUMMY );
   I136 : AFIFOFLG
      Port Map ( clk=>rclk, holdoff=>N_9, one=>plus1, reset=>gnd,
                 rw=>pop, set=>rrst, two=>plus2, zero=>zero,
                 almost_on=>almostempty_DUMMY, flag_on=>empty_DUMMY );
   I_120 : DFFPA
      Port Map ( CLK=>rclk, D=>gnd, S=>rrst, Q=>N_9 );
   I_115 : GCNTE5_0
      Port Map ( CLK=>wclk, CLR=>wrst, EN=>N_4,
                 Q(4 downto 0)=>Waddr0(4 downto 0) );
   I_74 : RGEC5_1R
      Port Map ( CLK=>rclk, CLR=>rrst, D(4 downto 0)=>Raddr2(4 downto 0),
                 EN=>N_11, Q(4 downto 0)=>Raddr1(4 downto 0) );
   I_77 : RGEC5_2
      Port Map ( CLK=>wclk, CLR=>wrst, D(4 downto 0)=>Waddr3(4 downto 0),
                 EN=>N_3, Q(4 downto 0)=>Waddr2(4 downto 0) );
   I_78 : GCNTE5_2
      Port Map ( CLK=>rclk, CLR=>rrst, EN=>N_2,
                 Q(4 downto 0)=>Raddr2(4 downto 0) );
   I_79 : GCNTE5_3
      Port Map ( CLK=>wclk, CLR=>wrst, EN=>N_3,
                 Q(4 downto 0)=>Waddr3(4 downto 0) );
   I_128 : OR2I0
      Port Map ( A=>N_10, B=>N_9, Q=>N_2 );
   I_45 : OR2I0
      Port Map ( A=>N_10, B=>N_9, Q=>N_11 );
   I_84 : AND2I1
      Port Map ( A=>push, B=>full_DUMMY, Q=>N_3 );
   I_50 : AND2I1
      Port Map ( A=>push, B=>full_DUMMY, Q=>N_4 );
   I_69 : AND2I1
      Port Map ( A=>pop, B=>empty_DUMMY, Q=>N_10 );
   I_26 : ECOMP5
      Port Map ( A(4 downto 0)=>Waddr0(4 downto 0),
                 B(4 downto 0)=>Raddr2(4 downto 0), EQ=>plus2 );
   I_19 : ECOMP5
      Port Map ( A(4 downto 0)=>Waddr0(4 downto 0),
                 B(4 downto 0)=>Raddr1(4 downto 0), EQ=>plus1 );
   I_85 : ECOMP5
      Port Map ( A(4 downto 0)=>Waddr2(4 downto 0),
                 B(4 downto 0)=>Raddr1(4 downto 0), EQ=>minus1 );
   I_18 : ECOMP5
      Port Map ( A(4 downto 0)=>Waddr3(4 downto 0),
                 B(4 downto 0)=>Raddr1(4 downto 0), EQ=>minus2 );
   I_17 : ECOMP5
      Port Map ( A(4 downto 0)=>Waddr2(4 downto 0),
                 B(4 downto 0)=>Raddr2(4 downto 0), EQ=>zero );

end SCHEMATIC;

library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE.all;

entity cardbus_5632 is
      Port (    ir_n : In    STD_LOGIC;
                lclk : In    STD_LOGIC;
                 ren : Out   STD_LOGIC;
                  oe : Out   STD_LOGIC;
                or_n : In    STD_LOGIC;
                 wen : Out   STD_LOGIC;
                  ld : Out   STD_LOGIC;
               pae_n : In    STD_LOGIC;
               paf_n : In    STD_LOGIC;
                 lad : InOut STD_LOGIC_VECTOR (31 downto 0);
                 led : Out   STD_LOGIC_VECTOR (7 downto 0);
                 mrs : Out   STD_LOGIC;
             pad_CIS_ADR : Out   STD_LOGIC_VECTOR (9 downto 2);
             pad_CIS_data : In    STD_LOGIC_VECTOR (31 downto 0);
                REQN : Out   STD_LOGIC;
               SERRN : Out   STD_LOGIC;
               PERRN : InOut STD_LOGIC;
                 PAR : InOut STD_LOGIC;
                GNTN : In    STD_LOGIC;
               STOPN : InOut STD_LOGIC;
               IDSEL : In    STD_LOGIC;
             DEVSELN : InOut STD_LOGIC;
                RSTN : In    STD_LOGIC;
               TRDYN : InOut STD_LOGIC;
                 CLK : In    STD_LOGIC;
               IRDYN : InOut STD_LOGIC;
              FRAMEN : InOut STD_LOGIC;
                CBEN : InOut STD_LOGIC_VECTOR (3 downto 0);
                  AD : InOut STD_LOGIC_VECTOR (31 downto 0);
               INTAN : Out   STD_LOGIC;
             pad_CBLOCK_n : In    STD_LOGIC;
             pad_PWM : In    STD_LOGIC;
             pad_BAM : In    STD_LOGIC;
              pad_wp : In    STD_LOGIC;
             pad_ready : In    STD_LOGIC;
             pad_bvd : In    STD_LOGIC_VECTOR (2 downto 1);
             pad_gwake : In    STD_LOGIC;
             pad_intr : In    STD_LOGIC;
             pad_clk_resume : In    STD_LOGIC;
             pad_CCLKRUN_n : InOut STD_LOGIC;
             pad_owner_access : Out   STD_LOGIC;
             pad_locked : Out   STD_LOGIC;
             pad_clk_stopped : Out   STD_LOGIC;
             pad_CAUDIO : Out   STD_LOGIC;
             pad_CSTSCHG : Out   STD_LOGIC;
             pad_CINT_n : Out   STD_LOGIC );
end cardbus_5632;


architecture SCHEMATIC of cardbus_5632 is

   signal Mst_WrData : STD_LOGIC_VECTOR (31 downto 0);
   signal Mst_WrData_FIFO : STD_LOGIC_VECTOR (31 downto 0);
   signal  Usr_CBE : STD_LOGIC_VECTOR (3 downto 0);
   signal Cfg_CacheLineSize : STD_LOGIC_VECTOR (7 downto 2);
   signal Cfg_RdData : STD_LOGIC_VECTOR (31 downto 0);
   signal      ADR : STD_LOGIC_VECTOR (9 downto 0);
   signal Cfg_LatCnt : STD_LOGIC_VECTOR (7 downto 0);
   signal   Mst_BE : STD_LOGIC_VECTOR (3 downto 0);
   signal Mst_RdAd : STD_LOGIC_VECTOR (31 downto 0);
   signal Mst_WrAd : STD_LOGIC_VECTOR (31 downto 0);
   signal  PCI_Cmd : STD_LOGIC_VECTOR (3 downto 0);
   signal WrBuff_in : STD_LOGIC_VECTOR (31 downto 0);
   signal RdBuff_out : STD_LOGIC_VECTOR (31 downto 0);
   signal mem_RdData : STD_LOGIC_VECTOR (31 downto 0);
   signal Usr_RdData : STD_LOGIC_VECTOR (31 downto 0);
   signal cstschg_regs : STD_LOGIC_VECTOR (31 downto 0);
   signal RdBuff_mux : STD_LOGIC_VECTOR (31 downto 0);
   signal      WrD : STD_LOGIC_VECTOR (31 downto 0);
   signal Mst_BE_FIFO : STD_LOGIC_VECTOR (3 downto 0);
   signal Mst_WrData_Reg : STD_LOGIC_VECTOR (31 downto 0);
   signal   ledout : STD_LOGIC_VECTOR (7 downto 0);
   signal  mxledoi : STD_LOGIC_VECTOR (7 downto 0);
   signal   mxledo : STD_LOGIC_VECTOR (7 downto 0);
   signal Usr_RdDataIn : STD_LOGIC_VECTOR (31 downto 0);
	constant 		GND_bit : STD_LOGIC := '0';
   signal CIS_data : STD_LOGIC_VECTOR (31 downto 0);
   signal Cfg_CmdReg : STD_LOGIC_VECTOR (15 downto 0);
   signal   bvd_ps : STD_LOGIC_VECTOR (2 downto 1);
   signal Usr_Addr_WrData : STD_LOGIC_VECTOR (31 downto 0);
   signal   locked : STD_LOGIC;
   signal owner_access : STD_LOGIC;
   signal clk_stopped : STD_LOGIC;
   signal   CINT_n : STD_LOGIC;
   signal  CSTSCHG : STD_LOGIC;
   signal   CAUDIO : STD_LOGIC;
   signal CCLKRUN_n_in : STD_LOGIC;
   signal CCLKRUN_n_out : STD_LOGIC;
   signal CCLKRUN_n_oe : STD_LOGIC;
   signal CBLOCK_n : STD_LOGIC;
   signal   PWM_in : STD_LOGIC;
   signal   BAM_in : STD_LOGIC;
   signal    wp_ps : STD_LOGIC;
   signal ready_ps : STD_LOGIC;
   signal gwake_ps : STD_LOGIC;
   signal  intr_ps : STD_LOGIC;
   signal clk_resume : STD_LOGIC;
   signal Usr_Stop : STD_LOGIC;
   signal Usr_Last_Cycle_D1 : STD_LOGIC;
   signal     N_18 : STD_LOGIC;
   signal     N_19 : STD_LOGIC;
   signal     N_20 : STD_LOGIC;
   signal     s1s0 : STD_LOGIC;
   signal     s0en : STD_LOGIC;
   signal     s1en : STD_LOGIC;
   signal  DMAWrEn : STD_LOGIC;
   signal  DMARdEn : STD_LOGIC;
   signal ledcntrl : STD_LOGIC;
   signal   BEfifo : STD_LOGIC;
   signal BEFIFO_fulln : STD_LOGIC;
   signal     N_21 : STD_LOGIC;
   signal     N_22 : STD_LOGIC;
   signal     N_23 : STD_LOGIC;
   signal     N_24 : STD_LOGIC;
   signal     N_25 : STD_LOGIC;
   signal WrBuff_almost_full : STD_LOGIC;
   signal   re_dly : STD_LOGIC;
   signal RdBuff_fullN : STD_LOGIC;
   signal RdBuff_almost_empty : STD_LOGIC;
   signal   we_int : STD_LOGIC;
   signal     N_26 : STD_LOGIC;
   signal     N_27 : STD_LOGIC;
   signal     N_28 : STD_LOGIC;
   signal     N_29 : STD_LOGIC;
   signal     N_30 : STD_LOGIC;
   signal     N_31 : STD_LOGIC;
   signal     N_32 : STD_LOGIC;
   signal Prog_Stop : STD_LOGIC;
   signal  CIS_sel : STD_LOGIC;
   signal cstschg_rdy : STD_LOGIC;
   signal  Mem_Rdy : STD_LOGIC;
   signal RdData_MUX_sel : STD_LOGIC;
   signal CardBus_BAR : STD_LOGIC;
   signal Usr_Read : STD_LOGIC;
   signal PCI_FRAME_D1 : STD_LOGIC;
	constant 		VCC : STD_LOGIC := '1';
   signal      ldn : STD_LOGIC;
   signal   we_out : STD_LOGIC;
   signal fifo_oe_n : STD_LOGIC;
   signal   re_out : STD_LOGIC;
   signal  fpga_oe : STD_LOGIC;
   signal WrBuff_fullN : STD_LOGIC;
   signal local_clock : STD_LOGIC;
   signal Mst_WrData_Valid : STD_LOGIC;
   signal DMA_Error : STD_LOGIC;
   signal Usr_MstRdAd_Sel : STD_LOGIC;
   signal local_reset : STD_LOGIC;
   signal Usr_MstWrAd_Sel : STD_LOGIC;
   signal Mst_One_Read : STD_LOGIC;
   signal RdBuff_empty_sync : STD_LOGIC;
   signal Mst_Xfer_D1 : STD_LOGIC;
   signal Mst_Two_Reads : STD_LOGIC;
   signal loc_sync_reset : STD_LOGIC;
   signal WrBuff_emptyN : STD_LOGIC;
   signal  LocalEn : STD_LOGIC;
   signal WrBuff_almost_empty : STD_LOGIC;
   signal Mst_WrBurst_Done : STD_LOGIC;
   signal Mst_LatCntEn : STD_LOGIC;
   signal Mst_RdBurst_Done : STD_LOGIC;
   signal Mst_Rd_Term_Sel : STD_LOGIC;
	constant 		GND : STD_LOGIC := '0';
   signal Mst_RdData_Valid : STD_LOGIC;
   signal Cfg_PERR_Det : STD_LOGIC;
   signal Cfg_MstPERR_Det : STD_LOGIC;
   signal Cfg_SERR_Sig : STD_LOGIC;
   signal   irn_in : STD_LOGIC;
   signal  pafn_in : STD_LOGIC;
   signal  paen_in : STD_LOGIC;
   signal   orn_in : STD_LOGIC;
   signal RdBuff_empty : STD_LOGIC;
   signal RdBuff_full : STD_LOGIC;
   signal WrBuff_empty : STD_LOGIC;
   signal WrBuff_full : STD_LOGIC;
   signal Mst_Tabort_Det : STD_LOGIC;
   signal Mst_TTO_Det : STD_LOGIC;
   signal  Usr_Rdy : STD_LOGIC;
   signal Usr_Write : STD_LOGIC;
   signal Cfg_Write : STD_LOGIC;
   signal Cfg_Stop : STD_LOGIC;
   signal Mst_Data_Sel : STD_LOGIC;
   signal Usr_Adr_Valid : STD_LOGIC;
   signal Usr_Adr_Inc : STD_LOGIC;