fifocont.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

--------------------------------------------------------------------------------
--
-- File : fifocont.vhd
-- Last Modification: 06/26/2001
--
-- Created In SpDE Version: SpDE 8.22
-- Author :	Richard Yuan, QuickLogic Corporation
-- Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--	
-- Description :
--	This is the controller of the external IDT FIFO chip.
--
-- Hierarchy:
--	This file represents the fifocont block in pci5(3/4)32_208.sch.
--
-- History:	
--	Date	        Author					Version
--  06/26/01		Richard Yuan			1.0
--		- Header reorganized to conform to coding standard.
--
--------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

entity fifocont is
 
port
    (
    clk, clr: in std_logic;
    we, we_int, re, re_dly, fpga_oe, idt_fifo_oe_n: out std_logic;
    idt_fifo_full, idt_fifo_af_n, idt_fifo_empty, idt_fifo_ae_n: in std_logic;
    rbuff_empty, rbuff_ae, wbuff_full, wbuff_af: in std_logic;
    ldn: out std_logic
    );
end fifocont;

architecture behavioral of fifocont is

signal fstate: std_logic_vector(5 downto 0); -- synthesis syn_preserve = 1
signal init, we_dly, re_int: std_logic;

signal we_int_local: std_logic;

constant fifo_read : std_logic_vector := "110010";
constant prep_read : std_logic_vector := "100000";
constant fifo_write: std_logic_vector := "001101";
constant prep_write: std_logic_vector := "000100";
constant idle      : std_logic_vector := "000000";

begin
    
    we_int <= we_int_local;
    
    process (clk, clr)
    begin
        if clr = '1' then fstate <= idle;
        elsif clk'event and clk = '1' then
            case fstate is 
                when idle       => if idt_fifo_full = '0' and rbuff_empty = '0' then
                                       fstate <= prep_write;
                                   elsif idt_fifo_empty = '0' and wbuff_full = '0' then
                                       fstate <= prep_read;
                                   else 
                                       fstate <= idle; 
                                   end if;
                when prep_write => if idt_fifo_full = '0' then 
                                       fstate <= fifo_write;
                                   else
                                       fstate <= idle;
                                   end if;
                when fifo_write => if idt_fifo_af_n = '0' or rbuff_ae = '1' then
                                       fstate <= idle;
                                   else 
                                       fstate <= fifo_write;
                                   end if;
                when prep_read  => if idt_fifo_empty = '0' and wbuff_full = '0' then
                                       fstate <= fifo_read;
                                   else 
                                       fstate <= idle;
                                   end if;
                when fifo_read  => if idt_fifo_ae_n = '0' or wbuff_af = '1' then
                                       fstate <= idle;
                                   else
                                       fstate <= fifo_read;
                                   end if;
                when others     => fstate <= (others =>'X');
            end case;
        end if;
    end process;

    -- optimized state assignment allows direct state bit mapping to outputs
    we            <= fstate(0);
    we_int_local  <= fstate(3);
    re            <= fstate(1);
    re_int        <= fstate(4);
    fpga_oe       <= fstate(2);
    idt_fifo_oe_n <= fstate(2);

    -- make sure ldn is active for the first two we pulses
    process (clk, clr)
    begin
        if clr = '1' then init <= '0';
        elsif clk'event and clk = '1' then
            if we_dly = '1' and we_int_local = '1' then init <= '1'; end if;
        end if;
    end process; 

    process  (clk, clr)
    begin
        if clr = '1' then we_dly <= '0';
        elsif clk'event and clk = '1' then
            if we_int_local = '1' then we_dly <= '1'; end if;
        end if;
    end process;

    process  (clk, clr)
    begin
        if clr = '1' then ldn <= '0';
        elsif clk'event and clk = '1' then
            if init = '1' then ldn <= '1'; end if;
        end if;
    end process;

    process  (clk, clr)
    begin
        if clr = '1' then re_dly <= '0';
        elsif clk'event and clk = '1' then
            if wbuff_full = '0' then re_dly <= re_int; end if;
        end if;
    end process;

end behavioral;