cardbus_5632aldec.do

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

#------------------------------------------------------------------------------
#
# File : cardbus_5632aldec.do
# Last Modification: 5/4/2004
#
# Created In SpDE Version: SpDE 9.3
# Author :	Richard Yuan, QuickLogic Corporation
# Copyright (C) 2002, Licensed customers of QuickLogic may copy and modify
# this file for use in designing with QuickLogic devices only.
#	
# Description :
#	This script runs QL5632-33 vhdl reference design prelayout simulation 
#       in Active-HDL.
#	 
# History:	
#	Date	        Author					Version
#	06/26/01		Richard Yuan			1.0
#		- Header added to conform to coding standard.
#	07/25/02	Jens Niemann				1.1
#		- Some variables defined to change all devices and packages 
#		  in one block
#	11/18/02	Claire Pian Tu				1.2
#		- Added cmd_monitor test bench and wave signals
#	05/04/04	Claire Pian Tu				1.3
#		- Modified for CardBus IP
#----------------------------------------------------------------------------


#--------Instructions, that can be used with Aldec Macro Language------------
# cd ..  for going one level down
# cd directoryname for going one level up
# pwd for checking current directory
# alternatively you can use the old DOS instruction with adding 
# an exclamation mark
# e.g.  !dir *.vhd
# $dsn means the directory in which the do file is

# XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
# Design Variable setting change in this block the paths and filenames

# Change this path to your source file directory
#set curpath c:\pasic\design\reference\pci5632_280\vhdl
set curpath d:\project\CardBus\Source\vhdl

#set primitivepath c:\pasic\spde\data\ql5632-33\pci32_25um
set primitivepath d:\pasic\spde\data\ql5632-33\pci32_25um

#set macropath c:\pasic\spde\data
set macropath d:\pasic\spde\data

set design_name cardbus_5632
set adf_file_name cardbus_5632.adf 
set config_space_module_pkg cfgtaddr_5632_280_pkg.vhd
set config_space_module cfgtaddr_cardbus.vhd
set top_level_module cardbus_5632.vhd
set cfg_comp_tb pci_comp_5632.tb
set top_level_tb cardbus_5632.tb
# XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

# create a new design in the current directory in Active-HDL and open it
createdesign $design_name $curpath
opendesign $adf_file_name
# create work library
alib work
set worklib work

# end of Active-HDL design settings
# all files used must be added first, then vhdl files are compiled


# compile QuickLogic macros library
addfile -vhdl $macropath/macros.vhd
acom $macropath/macros.vhd

# compile QuickLogic RAM primitives
addfile -vhdl $curpath/ram128x18_25um.vhd
acom $curpath/ram128x18_25um.vhd
addfile -vhdl $curpath/ram128x9.vhd
acom $curpath/ram128x9.vhd

# compile QL5632-33 PCI core simulation model files
addfile -vhdl $primitivepath/v1_2/pci3233_25um.vhd
acom $primitivepath/v1_2/pci3233_25um.vhd
addfile -vhdl $primitivepath/pci32_25um.vhd
acom $primitivepath/pci32_25um.vhd



# compile QL5632-33 reference design files
addfile -vhdl $curpath/r128x32_25um.vhd
acom $curpath/r128x32_25um.vhd
addfile -vhdl $curpath/r128a8.vhd
acom $curpath/r128a8.vhd
addfile -vhdl $curpath/r128x4_25um.vhd
acom $curpath/r128x4_25um.vhd
addfile -vhdl $curpath/ucnt7_25um.vhd
acom $curpath/ucnt7_25um.vhd
addfile -vhdl $curpath/updcnt7_25um.vhd
acom $curpath/updcnt7_25um.vhd
addfile -vhdl $curpath/cnt64.vhd
acom $curpath/cnt64.vhd
addfile -vhdl $curpath/lcnt64.vhd
acom $curpath/lcnt64.vhd
addfile -vhdl $curpath/f128x4_25um.vhd
acom $curpath/f128x4_25um.vhd
addfile -vhdl $curpath/dcount8.vhd
acom $curpath/dcount8.vhd
addfile -vhdl $curpath/dcount16.vhd
acom $curpath/dcount16.vhd
addfile -vhdl $curpath/gcnte5_0.vhd
acom $curpath/gcnte5_0.vhd
addfile -vhdl $curpath/gcnte5_2.vhd
acom $curpath/gcnte5_2.vhd
addfile -vhdl $curpath/gcnte5_3.vhd
acom $curpath/gcnte5_3.vhd
addfile -vhdl $curpath/rgec5_1r.vhd
acom $curpath/rgec5_1r.vhd
addfile -vhdl $curpath/rgec5_2.vhd
acom $curpath/rgec5_2.vhd
addfile -vhdl $curpath/CIS_decode.vhd
acom $curpath/CIS_decode.vhd
addfile -vhdl $curpath/$config_space_module_pkg
acom $curpath/$config_space_module_pkg
addfile -vhdl $curpath/$config_space_module
acom $curpath/$config_space_module
addfile -vhdl $curpath/cardbus_wrapper.vhd
acom $curpath/cardbus_wrapper.vhd
addfile -vhdl $curpath/dmacntrl.vhd
acom $curpath/dmacntrl.vhd
addfile -vhdl $curpath/dmaregrd.vhd
acom $curpath/dmaregrd.vhd
addfile -vhdl $curpath/fifocont.vhd
acom $curpath/fifocont.vhd
addfile -vhdl $curpath/initflgs.vhd
acom $curpath/initflgs.vhd
addfile -vhdl $curpath/$top_level_module
acom $curpath/$top_level_module


# compile test bench files
addfile -vhdl $curpath/utils_pkg.tb
acom $curpath/utils_pkg.tb
addfile -vhdl $curpath/clk_gen.tb
acom $curpath/clk_gen.tb
addfile -vhdl $curpath/idt_fifo.tb
acom $curpath/idt_fifo.tb
addfile -vhdl $curpath/pci_pack.tb
acom $curpath/pci_pack.tb
addfile -vhdl $curpath/pci_access.tb
acom $curpath/pci_access.tb
addfile -vhdl $curpath/pci_arb.tb
acom $curpath/pci_arb.tb
addfile -vhdl $curpath/pci_mast.tb
acom $curpath/pci_mast.tb
addfile -vhdl $curpath/pci_tar.tb
acom $curpath/pci_tar.tb
# file used in protocol checking
# this file must be copied to the local src directory (which is the -c)
addfile -c -txt $curpath/bus_chk.mem
addfile -vhdl $curpath/proto_chk.tb
acom $curpath/proto_chk.tb
addfile -vhdl $curpath/byte_enable_test.tb
acom $curpath/byte_enable_test.tb
addfile -vhdl $curpath/pci_cmd_test.tb
acom $curpath/pci_cmd_test.tb
addfile -vhdl $curpath/$cfg_comp_tb
acom $curpath/$cfg_comp_tb
addfile -vhdl $curpath/cmd_monitor.tb
acom $curpath/cmd_monitor.tb
addfile -vhdl $curpath/CIS.tb
acom $curpath/CIS.tb
addfile -vhdl $curpath/cardbus_wrapper_test.tb
acom $curpath/cardbus_wrapper_test.tb
addfile -vhdl $curpath/$top_level_tb
acom $curpath/$top_level_tb


# start simulation with 100ps resolution
asim -t 100ps t t_arch
# open a waveform window
view wave
# add PCI signals
wave perrn
wave serrn
wave par
wave reqn
wave gntn
wave rstn
wave clk
wave idsel
wave -literal -hex ad
wave -literal -hex cben
wave framen
wave irdyn
wave devseln
wave trdyn
wave stopn

#cmd_monitor signals
wave -literal -hex cmd_mon_1/mem_address
wave cmd_mon_1/PCI_CMD
wave cmd_mon_1/PCI_CMD_l
wave cmd_mon_1/config_add

# run simulation till end
run -all