ram128x9.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

--128x4 RAM with Synchronous Write, both Synchronous and Asynchronous Read
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity RAM128X9 is
  port (WA, RA : in std_logic_vector (6 downto 0);
  	     WD : in std_logic_vector (8 downto 0);
  	     WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
  	     RD : out std_logic_vector (8 downto 0) );
end RAM128X9;

architecture arch of RAM128X9 is

attribute black_box : boolean;
attribute black_box of arch : architecture is true;

signal RAREG : std_logic_vector (6 downto 0);
signal RADDR : std_logic_vector (6 downto 0);
type memory_type is array (integer range <>) of std_logic_vector (8 downto 0);
signal mem : memory_type (0 to 127);

begin

WRITE : process (WCLK)
begin
   if Rising_Edge(WCLK) then       	     
      if (WE = '1') then
         mem(CONV_INTEGER(WA)) <= WD;
      end if;
   end if;
end process;

READ : process (RCLK)
begin
   if Rising_Edge(RCLK) then
      if (RE = '1') then
         RAREG <= RA;
      end if;
   end if;
end process;

assign_rd : process (RADDR, mem)
begin
   RD <= mem(CONV_INTEGER(RADDR));
end process;
RADDR <= RA when (ASYNCRD = '1') else RAREG;

end arch;