r128x32_25um.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

------------------------------------------------------------------------
-- File : r128x32_25um.vhd
-- Design Date: June 9, 1998
-- Creation Date: Tue May 07 10:53:25 2002

-- Created By SpDE Version: SpDE 9.3 Alpha Build3
-- Author: Ed Bezeg, Robert Maul, QuickLogic Corporation,
-- Copyright (C) 1998, Customers of QuickLogic may copy and modify this
-- file for use in designing QuickLogic devices only.
-- Description : This file is autogenerated structural code that describes
-- the connectivity of cascaded RAM blocks (called RAM banks) using
-- QuickLogic's RAM block resources.
------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

   -- inputs: =wa[6:0]=,=ra[6:0]=,=wd[31:0]=,we,re,wclk,rclk
   -- outputs: =rd[31:0]=
entity r128x32_25um is port (
   we,re,wclk,rclk : in std_logic;
   wa, ra : in std_logic_vector (6 downto 0);
   wd : in std_logic_vector (31 downto 0);
   rd : out std_logic_vector (31 downto 0));
end r128x32_25um;

architecture arch of r128x32_25um is
signal GND : std_logic;
signal VCC : std_logic;
signal WD_reg : std_logic_vector (35 downto 0);
signal RD_reg1 : std_logic_vector (17 downto 0);
signal RD_reg2 : std_logic_vector (17 downto 0);
attribute syn_black_box : boolean;
attribute syn_macro : integer;
component RAM128X18_25um
   port (WA, RA : in std_logic_vector (6 downto 0);
         WD : in std_logic_vector (17 downto 0);
         RD : out std_logic_vector (17 downto 0);
         WE, RE, WCLK, RCLK, ASYNCRD : in std_logic);
end component ;
attribute syn_black_box of RAM128X18_25UM : component is true;
attribute syn_macro of RAM128X18_25UM : component is 1;
begin
GND <= '0';
VCC <= '1';
rd <= ( RD_reg1(17 downto 0) & RD_reg2(17 downto 4) ) after 1 ns;
WD_reg <= ( wd & GND & GND & GND & GND ) after 1 ns;
r128x32_25umI1 : RAM128X18_25UM
   port map(WA => wa, RA => ra, WD => WD_reg(35 downto 18), RD => RD_reg1, 
            WE => we, RE => re,  WCLK => wclk, RCLK => rclk, ASYNCRD => GND);
r128x32_25umI2 : RAM128X18_25UM
   port map(WA => wa, RA => ra, WD => WD_reg(17 downto 0), RD => RD_reg2, 
            WE => we, RE => re,  WCLK => wclk, RCLK => rclk, ASYNCRD => GND);
end arch;