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📄 pci_comp_5632.tb

📁 VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用
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  	write(outline, string'("...Passed"));
  	writeline(output, outline);
else 
    --report "...*** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,1);

--report "Memory Write & Invalidate / Memory Read Multiple Test (Reserved Mode 11)";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Write & Invalidate / Memory Read Multiple Test (Reserved Mode 11)"));
writeline(output, outline);

address_reg <= std_logic_vector(unsigned(target_bar) + x"0103");

for i in 0 to 5 loop
	data_array(i) <= x"AAAAAAAA";
end loop;

be_array(0) <= "1100";
be_array(1) <= "1001";
be_array(2) <= "0011";
be_array(3) <= "0110";
be_array(4) <= "1100";
be_array(5) <= "1001";
be_array(6) <= "0011";
be_array(7) <= "0110";
be_array(8) <= "1100";
be_array(9) <= "1001";
be_array(10) <= "0011";
be_array(11) <= "0110";
be_array(12) <= "1100";
be_array(13) <= "1001";
be_array(14) <= "0011";
be_array(15) <= "0110";

wait_for_clocks(CLK,3);

pci_access(address_reg,data_reg,MEM_WR_INVALID,x"FF",6,1,0,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if Master_Abort = '0' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
else 
    --report "...*** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,1);

data_array(0) <= x"AAAA0000";
data_array(1) <= x"FFFFFFFC";
data_array(2) <= x"FFFFFFFC";
data_array(3) <= x"00000200";
data_array(4) <= x"00000000";
data_array(5) <= x"00000002";
for i in 0 to 5 loop
	be_array(i) <= x"F";
end loop;
be_array(4) <= "1000";

wait_for_clocks(CLK,3);

pci_access(address_reg,data_reg,MEM_READ_MULT,x"FF",6,1,0,0,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if Master_Abort = '0' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
else 
    --report "...*** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,1);

address_reg <= std_logic_vector(unsigned(target_bar) + x"3F0");

wait_for_clocks(CLK,5);
--report "Burst Accross the Device Boundary Test";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Burst Accross the Device Boundary Test"));
writeline(output, outline);

for i in 0 to 5 loop
	data_array(i) <= x"FFFFFFFF";
	be_array(i) <= x"F";
end loop;

clear_Disconnect <= '1';

wait_for_clocks(CLK,1);
clear_Disconnect <= '0';
wait_for_clocks(CLK,1);

pci_access(address_reg,data_reg,MEM_WRITE,x"FF",6,2,3,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if Disconnect_Detected = '1' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
	clear_Disconnect <= '1';
else 
    --report "...*** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
clear_Disconnect <= '0';

data_reg <= x"FFFFFFFFFFFFFFFF";

wait_for_clocks(CLK,4);
--report "Memory Read Address Parity Error Test: Target should assert SERRN";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Read Address Parity Error Test: Target should assert SERRN"));
writeline(output, outline);

pci_access(target_bar,data_reg,MEM_READ,x"FF",1,1,1,1,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);

if SERRN_Detected = '1' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
	clear_SERR <= '1';
else 
    --report "... *** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
clear_SERR <= '0';

wait_for_clocks(CLK,4);
--report "Memory Read Line Address Parity Error Test: Target should assert SERRN";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Read Line Address Parity Error Test: Target should assert SERRN"));
writeline(output, outline);

pci_access(target_bar,data_reg,MEM_READ_LINE,x"FF",1,1,1,1,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if SERRN_Detected = '1' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
	clear_SERR <= '1';
else 
    --report "... *** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
clear_SERR <= '0';

wait_for_clocks(CLK,4);
--report "Memory Read Multiple Address Parity Error Test: Target should assert SERRN";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Read Multiple Address Parity Error Test: Target should assert SERRN"));
writeline(output, outline);

pci_access(target_bar,data_reg,MEM_READ_MULT,x"FF",1,1,1,1,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);

if SERRN_Detected = '1' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
	clear_SERR <= '1';
else 
    --report "... *** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
clear_SERR <= '0';

wait_for_clocks(CLK,4);
--report "Memory Write Address Parity Error Test: Target should assert SERRN";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Write Address Parity Error Test: Target should assert SERRN"));
writeline(output, outline);

pci_access(target_bar,data_reg,MEM_WRITE,x"FF",1,1,1,1,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if SERRN_Detected = '1' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
	clear_SERR <= '1';
else 
    --report "... *** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
clear_SERR <= '0';

wait_for_clocks(CLK,4);

--report "Memory Write and Invalidate Address Parity Error Test: Target should assert SERRN";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Write and Invalidate Address Parity Error Test: Target should assert SERRN"));
writeline(output, outline);

pci_access(target_bar,data_reg,MEM_WR_INVALID,x"FF",1,1,1,1,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if SERRN_Detected = '1' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
	clear_SERR <= '1';
else 
    --report "... *** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
clear_SERR <= '0';

wait_for_clocks(CLK,4);
--report "Memory Write Data (Phase 1) Parity Error Test: Target should assert PERRN";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Write Data (Phase 1) Parity Error Test: Target should assert PERRN"));
writeline(output, outline);

clear_PERR <= '1';
wait_for_clocks(CLK,1);
clear_PERR <= '0';
wait_for_clocks(CLK,1);

pci_access(target_bar,data_reg,MEM_WRITE,x"FF",3,1,1,2,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if PERRN_Detected = '1' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
	clear_PERR <= '1';
else 
    --report "... *** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
clear_PERR <= '0';
wait_for_clocks(CLK,1);

--report "Memory Write Data (Phase 2) Parity Error Test: Target should assert PERRN";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Write Data (Phase 2) Parity Error Test: Target should assert PERRN"));
writeline(output, outline);

	wait_for_clocks(CLK,5);

	pci_access(target_bar,data_reg,MEM_WRITE,x"FF",3,1,1,3,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
	if PERRN_Detected = '1' then
		--report "... Passed";
  		write(outline, string'("...Passed"));
  		writeline(output, outline);
		clear_PERR <= '1';
	else 
	   --report "... *** Failed ***";
	   write(outline, string'("... *** Failed ***"));
	   writeline(output, outline);
	   pci_compliance_errors := pci_compliance_errors + 1;
	end if;

wait_for_clocks(CLK,1);
clear_PERR <= '0';
wait_for_clocks(CLK,1);

--report "Memory Write and Invalidate Data (Phase 1) Parity Error Test: Target should assert PERRN";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Write and Invalidate Data (Phase 1) Parity Error Test: Target should assert PERRN"));
writeline(output, outline);

	wait_for_clocks(CLK,5);
	clear_PERR <= '1';

wait_for_clocks(CLK,1);
clear_PERR <= '0';
wait_for_clocks(CLK,1);

	pci_access(target_bar,data_reg,MEM_WR_INVALID,x"FF",3,1,1,2,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
	if PERRN_Detected = '1' then
		--report "... Passed";
  		write(outline, string'("...Passed"));
  		writeline(output, outline);
		clear_PERR <= '1';
	else 
	   --report "... *** Failed ***";
	   write(outline, string'("... *** Failed ***"));
	   writeline(output, outline);
	   pci_compliance_errors := pci_compliance_errors + 1;
	end if;

wait_for_clocks(CLK,1);
clear_PERR <= '0';
wait_for_clocks(CLK,1);

--report "Memory Write and Invalidate Data (Phase 2) Parity Error Test: Target should assert PERRN";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Write and Invalidate Data (Phase 2) Parity Error Test: Target should assert PERRN"));
writeline(output, outline);

	wait_for_clocks(CLK,5);

	pci_access(target_bar,data_reg,MEM_WR_INVALID,x"FF",3,1,1,3,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
	if PERRN_Detected = '1' then
		--report "... Passed";
  		write(outline, string'("...Passed"));
  		writeline(output, outline);
		clear_PERR <= '1';
	else 
	   --report "... *** Failed ***";
	   write(outline, string'("... *** Failed ***"));
	   writeline(output, outline);
	   pci_compliance_errors := pci_compliance_errors + 1;
	end if;


wait_for_clocks(CLK,1);
clear_PERR <= '0';
wait_for_clocks(CLK,1);


--report "End of PCI compliance tests. " & integer'image(pci_compliance_errors) & " errors detected.";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] End of PCI compliance tests. "));
write(outline, integer'image(pci_compliance_errors));
write(outline, string'(" errors detected."));
writeline(output, outline);


end pci_comp;

end package body pci_comp_package;
1234

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