pci_comp_5632.tb

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

	be_array(i) <= x"F";
end loop;

pci_access(target_bar,data_reg,MEM_WRITE,x"FF",256,0,0,0,'0','1',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);

if Master_Abort = '0' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
else 
    --report "...*** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,3);

data_array(64) <= x"FFFFFFFF";
data_array(65) <= x"FFFFFFFC";
data_array(66) <= x"FFFFFFFC";
data_array(67) <= x"FFFFFF00";
data_array(68) <= x"00000000";
data_array(69) <= x"00000007";
data_array(70) <= x"007701FF";
be_array(68) <= "1000";

wait_for_clocks(CLK,5);

pci_access(target_bar,data_reg,MEM_READ,x"FF",256,0,0,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if Master_Abort = '0' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
else 
    --report "...*** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,3);

--report "Memory Write & Invalidate / Memory Read Line Test";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Write & Invalidate / Memory Read Line Test"));
writeline(output, outline);

for i in 0 to 15 loop
	data_array(i) <= x"00000000";
end loop;

be_array(0) <= "0011";
be_array(1) <= "0110";
be_array(2) <= "1100";
be_array(3) <= "1001";
be_array(4) <= "0011";
be_array(5) <= "0110";
be_array(6) <= "1100";
be_array(7) <= "1001";
be_array(8) <= "0011";
be_array(9) <= "0110";
be_array(10) <= "1100";
be_array(11) <= "1001";
be_array(12) <= "0011";
be_array(13) <= "0110";
be_array(14) <= "1100";
be_array(15) <= "1001";

-- Beginning of DMA Registers in 5x32 memory map
address_reg <= std_logic_vector(unsigned(target_bar) + x"0100");

pci_access(address_reg,data_reg,MEM_WR_INVALID,x"FF",6,2,3,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);

if Master_Abort = '0' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
else 
    --report "...*** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,1);

data_array(0) <= x"FFFF0000";
data_array(1) <= x"FFFFFFFC";
data_array(2) <= x"FFFFFFFC";
data_array(3) <= x"00FFFF00";
data_array(4) <= x"00000000";
data_array(5) <= x"00000007";

for i in 0 to 5 loop
	be_array(i) <= x"F";
end loop;
be_array(4) <= "1000";

wait_for_clocks(CLK,3);

pci_access(address_reg,data_reg,MEM_READ_LINE,x"FF",6,2,3,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if Master_Abort = '0' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
else 
    --report "...*** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;


wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,3);

--report "Memory Write & Invalidate / Memory Read Multiple Test";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Write & Invalidate / Memory Read Multiple Test"));
writeline(output, outline);

for i in 0 to 5 loop
	data_array(i) <= x"AAAAAAAA";
end loop;

be_array(0) <= "1100";
be_array(1) <= "1001";
be_array(2) <= "0011";
be_array(3) <= "0110";
be_array(4) <= "1100";
be_array(5) <= "1001";
be_array(6) <= "0011";
be_array(7) <= "0110";
be_array(8) <= "1100";
be_array(9) <= "1001";
be_array(10) <= "0011";
be_array(11) <= "0110";
be_array(12) <= "1100";
be_array(13) <= "1001";
be_array(14) <= "0011";
be_array(15) <= "0110";

-- Beginning of DMA Registers in 5x32 memory map
address_reg <= std_logic_vector(unsigned(target_bar) + x"0100");

pci_access(address_reg,data_reg,MEM_WR_INVALID,x"FF",6,1,0,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if Master_Abort = '0' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
else 
    --report "...*** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,1);

data_array(0) <= x"AAAA0000";
data_array(1) <= x"FFFFFFFC";
data_array(2) <= x"FFFFFFFC";
data_array(3) <= x"00AAAA00";
data_array(4) <= x"00000000";
data_array(5) <= x"00000002";
for i in 0 to 5 loop
	be_array(i) <= x"F";
end loop;
be_array(4) <= "1000";

wait_for_clocks(CLK,3);

pci_access(address_reg,data_reg,MEM_READ_MULT,x"FF",6,1,0,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);

if Master_Abort = '0' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
else 
    --report "...*** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,1);

data_array(0) <= x"001011E3";
data_array(1) <= x"02000162";
data_array(2) <= x"02000001";
data_array(3) <= x"00001000";
data_array(4) <= x"22000000";
for i in 0 to 5 loop
	be_array(i) <= x"F";
end loop;

address_reg <= x"0000000000000000";
data_reg <= x"0000000000000000";

wait_for_clocks(CLK,3);

--report "Resetting the Device for Memory Read/Write Test";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Resetting the Device for Memory Read/Write Test"));
writeline(output, outline);

pci_access(address_reg,data_reg,CONFIG_WRITE,x"FF",5,2,3,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);

if Master_Abort = '0' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
else 
    --report "...*** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,1);

-- Beginning of DMA Registers in 5x32 memory map
address_reg <= std_logic_vector(unsigned(target_bar) + x"0101");

wait_for_clocks(CLK,3);

--report "Memory Write/Memory Read Test (Reserved Mode 01)";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Write/Memory Read Test (Reserved Mode 01)"));
writeline(output, outline);

for i in 0 to 5 loop
	data_array(i) <= x"FFFFFFFF";
	be_array(i) <= x"F";
end loop;

pci_access(address_reg,data_reg,MEM_WRITE,x"FF",6,2,3,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);

if Master_Abort = '0' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
else 
    --report "...*** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,1);

data_array(0) <= x"FFFFFFFF";
data_array(1) <= x"FFFFFFFC";
data_array(2) <= x"FFFFFFFC";
data_array(3) <= x"FFFFFF00";
data_array(4) <= x"00000000";
data_array(5) <= x"00000007";
be_array(4) <= "1000";

wait_for_clocks(CLK,3);

pci_access(address_reg,data_reg,MEM_READ,x"FF",6,2,3,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if Master_Abort = '0' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
else 
    --report "...*** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,1);


--report "Memory Write & Invalidate / Memory Read Line Test (Reserved Mode 10)";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Write & Invalidate / Memory Read Line Test (Reserved Mode 10)"));
writeline(output, outline);

for i in 0 to 5 loop
	data_array(i) <= x"00000000";
end loop;

be_array(0) <= "0011";
be_array(1) <= "0110";
be_array(2) <= "1100";
be_array(3) <= "1001";
be_array(4) <= "0011";
be_array(5) <= "0110";
be_array(6) <= "1100";
be_array(7) <= "1001";
be_array(8) <= "0011";
be_array(9) <= "0110";
be_array(10) <= "1100";
be_array(11) <= "1001";
be_array(12) <= "0011";
be_array(13) <= "0110";
be_array(14) <= "1100";
be_array(15) <= "1001";

address_reg <= std_logic_vector(unsigned(target_bar) + x"0102");

wait_for_clocks(CLK,3);

pci_access(address_reg,data_reg,MEM_WR_INVALID,x"FF",4,2,3,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if Master_Abort = '0' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
else 
    --report "...*** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,1);

data_array(0) <= x"FFFF0000";
data_array(1) <= x"FFFFFFFC";
data_array(2) <= x"FFFFFFFC";
data_array(3) <= x"00FFFF00";
data_array(4) <= x"00000000";
data_array(5) <= x"00000007";
for i in 0 to 5 loop
	be_array(i) <= x"F";
end loop;
be_array(4) <= "1000";

wait_for_clocks(CLK,3);

pci_access(address_reg,data_reg,MEM_READ_LINE,x"FF",6,2,3,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if Master_Abort = '0' then
	--report "... Passed";