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📄 pci_comp_5632.tb

📁 VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用
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1234 
writeline(output, outline);

address_reg <= x"0000000000000000";
data_reg <= x"0000000000000000";
wait_for_clocks(CLK,5);
pci_access(target_bar,data_reg,CONFIG_WRITE,x"FF",16,2,3,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);

if Master_Abort = '0' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
else
    --report "...*** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

address_reg <= x"0000000000000001";
data_reg <= x"0000000000000000";

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,3);

--report "Config Write Type 1: Target should NOT respond";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Config Write Type 1: Target should NOT respond."));
writeline(output, outline);

pci_access(address_reg,data_reg,CONFIG_WRITE,x"FF",16,2,3,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);

if Master_Abort = '0' then
	--report "... *** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
else
	--report "...Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
end if;

address_reg <= x"0000000000000002";

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,3);

--report "Config Write Type X2: Target should NOT respond";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Config Write Type X2: Target should NOT respond."));
writeline(output, outline);

pci_access(address_reg,data_reg,CONFIG_WRITE,x"FF",16,2,3,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);

if Master_Abort = '0' then
	--report "... *** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
else
	--report "...Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
end if;

address_reg <= x"0000000000000003";

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,3);

--report "Config Write Type X3: Target should NOT respond";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Config Write Type X3: Target should NOT respond."));
writeline(output, outline);

pci_access(address_reg,data_reg,CONFIG_WRITE,x"FF",16,2,3,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if Master_Abort = '0' then
	--report "... *** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
else
	--report "...Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,1);

data_array(0) <= x"001E11E3";
data_array(1) <= x"0280015E";
data_array(2) <= x"FF000000";
data_array(3) <= x"0000FFFC";
data_array(4) <= x"FFFFFC00";
data_array(5) <= x"00000000";
data_array(6) <= x"00000000";
data_array(7) <= x"00000000";
data_array(8) <= x"00000000";
data_array(9) <= x"00000000";
data_array(10) <= x"00000000";
data_array(11) <= x"000211E3";
data_array(12) <= x"00000000";
data_array(13) <= x"00000000";
data_array(14) <= x"00000000";
data_array(15) <= x"10080000";


address_reg <= x"0000000000000000";

wait_for_clocks(CLK,3);

--report "Config Read Type 0: Target should respond";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Config Read Type 0: Target should respond."));
writeline(output, outline);

pci_access(address_reg,data_reg,CONFIG_READ,x"FF",16,2,3,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);

if Master_Abort = '0' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
else 
    --report "...*** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,1);

address_reg <= x"0000000000000001";
data_reg <= x"0000000000000000";

wait_for_clocks(CLK,3);

--report "Config Read Type 1: Target should NOT respond";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Config Read Type 1: Target should NOT respond."));
writeline(output, outline);

pci_access(address_reg,data_reg,CONFIG_READ,x"FF",16,2,3,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if Master_Abort = '0' then
	--report "... *** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
else
	--report "...Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,1);

address_reg <= x"0000000000000002";

wait_for_clocks(CLK,3);

--report "Config Read Type X2: Target should NOT respond";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Config Read Type X2: Target should NOT respond."));
writeline(output, outline);

pci_access(address_reg,data_reg,CONFIG_READ,x"FF",16,2,3,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if Master_Abort = '0' then
	--report "... *** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
else
	--report "...Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,1);

address_reg <= x"0000000000000003";

wait_for_clocks(CLK,3);

--report "Config Read Type X3: Target should NOT respond";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Config Read Type X3: Target should NOT respond."));
writeline(output, outline);

pci_access(address_reg,data_reg,CONFIG_READ,x"FF",16,2,3,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if Master_Abort = '0' then
	--report "... *** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
else
	--report "...Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,1);

for i in 0 to 15 loop
	data_array(i) <= x"00000000";
end loop;

be_array(0) <= "1000";
be_array(1) <= "0001";
be_array(2) <= "0010";
be_array(3) <= "0100";
be_array(4) <= "1000";
be_array(5) <= "0001";
be_array(6) <= "0010";
be_array(7) <= "0100";
be_array(8) <= "1000";
be_array(9) <= "0001";
be_array(10) <= "0010";
be_array(11) <= "0100";
be_array(12) <= "1000";
be_array(13) <= "0001";
be_array(14) <= "0010";
be_array(15) <= "0100";

--report "Config Write Type 0 (Byte Enable Test): Target should respond";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Config Write Type 0 (Byte Enable Test): Target should respond."));
writeline(output, outline);


address_reg <= x"0000000000000000";
data_reg <= x"0000000000000000";

wait_for_clocks(CLK,3);

pci_access(address_reg,data_reg,CONFIG_WRITE,x"FF",16,2,3,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if Master_Abort = '0' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
else
    --report "...*** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,1);

data_array(0) <= x"001E11E3";
data_array(1) <= x"02800100";
data_array(2) <= x"FF000000";
data_array(3) <= x"0000FFFC";
data_array(4) <= x"00FFFC00";
data_array(5) <= x"00000000";
data_array(6) <= x"00000000";
data_array(7) <= x"00000000";
data_array(8) <= x"00000000";
data_array(9) <= x"00000000";
data_array(10) <= x"00000000";
data_array(11) <= x"000211E3";
data_array(12) <= x"00000000";
data_array(13) <= x"00000000";
data_array(14) <= x"00000000";
data_array(15) <= x"10080000";

for i in 0 to 15 loop
	be_array(i) <= x"F";
end loop;

address_reg <= x"0000000000000000";

wait_for_clocks(CLK,3);

--report "Config Read Type 0 (Byte Enable Test): Target should respond";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Config Read Type 0 (Byte Enable Test): Target should respond."));
writeline(output, outline);

pci_access(address_reg,data_reg,CONFIG_READ,x"FF",16,2,3,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);

if Master_Abort = '0' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
else
    --report "...*** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,1);

address_reg <= x"0000000000000000";
data_array(0) <= x"001011E3";
data_array(1) <= x"02800162";
data_array(2) <= x"FF000001";
data_array(3) <= x"00004000";
data_array(4) <= x"22000000";
target_bar <= x"0000000022000000";

wait_for_clocks(CLK,3);

--report "Resetting the Device for Memory Read/Write Test";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Resetting the Device for Memory Read/Write Test"));
writeline(output, outline);

pci_access(address_reg,data_reg,CONFIG_WRITE,x"FF",5,2,3,0,'0','0',
           master1_start_bit,master1_done_bit,master1_addr,master1_command,
           master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
           master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);

if Master_Abort = '0' then
	--report "... Passed";
  	write(outline, string'("...Passed"));
  	writeline(output, outline);
else 
    --report "...*** Failed ***";
  	write(outline, string'("... *** Failed ***"));
  	writeline(output, outline);
	pci_compliance_errors := pci_compliance_errors + 1;
end if;

wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,3);

--report "Memory Write/Memory Read Test";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Memory Write/Memory Read Test"));
writeline(output, outline);

for i in 0 to 255 loop
	data_array(i) <= x"FFFFFFFF";
1234

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