📄 pci_comp_5632.tb
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--
-- File : pci_comp_5632.tb
-- Last Modification: 06/26/2001
--
-- Created In SpDE Version: SpDE 9.3
-- Author : Richard Yuan, QuickLogic Corporation
-- Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--
-- Description :
-- PCI target tests of the PCI compliance test suite.
--
-- Hierarchy:
-- This file provides a package to be used by pci5(3/4)32_208.tb.
--
-- History:
-- Date Author Version
-- 10/14/00 Richard Yuan 1.0
-- - Initial release. Modified from 5032 version.
-- 06/26/01 Richard Yuan 1.1
-- - Header reorganized to conform to coding standard.
-- 08/01/02 Jens Niemann 1.2
-- - modified for QL5632-208
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.pci_pack.all;
use work.pci_access_package.all;
package pci_comp_package is
procedure pci_comp (
signal address_reg : inout std_logic_vector(63 downto 0);
signal data_reg : inout std_logic_vector(63 downto 0);
signal target_bar : inout std_logic_vector(63 downto 0);
signal master_abort : in std_logic;
signal set_master_abort : out std_logic;
signal serrn_detected : in std_logic;
signal perrn_detected : in std_logic;
signal clear_serr : out std_logic;
signal clear_disconnect : out std_logic;
signal disconnect_detected : in std_logic;
signal clear_perr : out std_logic;
SIGNAL master1_start_bit : OUT std_logic;
SIGNAL master1_done_bit : IN std_logic;
SIGNAL master1_addr : OUT std_logic_vector(63 downto 0);
SIGNAL master1_command : OUT std_logic_vector(3 downto 0);
SIGNAL master1_dword_count : OUT integer;
SIGNAL master1_initial_data_delay : OUT integer;
SIGNAL master1_next_data_delay : OUT integer;
SIGNAL master1_bad_parity_phase: OUT integer;
SIGNAL master1_m64bit : OUT std_logic;
SIGNAL master1_quiet : OUT std_logic;
SIGNAL be_array : OUT BYTE_ARRAY_TYPE;
SIGNAL data_array : OUT DATA_ARRAY_TYPE;
SIGNAL CLK : IN std_logic
);
end pci_comp_package;
package body pci_comp_package is
procedure pci_comp (
signal address_reg : inout std_logic_vector(63 downto 0);
signal data_reg : inout std_logic_vector(63 downto 0);
signal target_bar : inout std_logic_vector(63 downto 0);
signal master_abort : in std_logic;
signal set_master_abort : out std_logic;
signal serrn_detected : in std_logic;
signal perrn_detected : in std_logic;
signal clear_serr : out std_logic;
signal clear_disconnect : out std_logic;
signal disconnect_detected : in std_logic;
signal clear_perr : out std_logic;
SIGNAL master1_start_bit : OUT std_logic;
SIGNAL master1_done_bit : IN std_logic;
SIGNAL master1_addr : OUT std_logic_vector(63 downto 0);
SIGNAL master1_command : OUT std_logic_vector(3 downto 0);
SIGNAL master1_dword_count : OUT integer;
SIGNAL master1_initial_data_delay : OUT integer;
SIGNAL master1_next_data_delay : OUT integer;
SIGNAL master1_bad_parity_phase: OUT integer;
SIGNAL master1_m64bit : OUT std_logic;
SIGNAL master1_quiet : OUT std_logic;
SIGNAL be_array : OUT BYTE_ARRAY_TYPE;
SIGNAL data_array : OUT DATA_ARRAY_TYPE;
SIGNAL CLK : IN std_logic
) is
variable i : integer;
variable pci_compliance_errors : integer;
variable outline : line;
begin
-- pci_access procedure
--
-- address : IN Destination address of access
-- data : IN write/expected data for one quadword transactions (see note)
-- pci_command : IN The PCI Command to be used for the transfer
-- byte_enable : IN write/expected byte enables for one quadWord transactions (see note)
-- dword_count : IN The number of dwords to transfer
-- initial_waitstates : IN waitstates to insert before 1st IRDYN assertion
--subsequent_waitstates : IN waitstates to insert after each data phase
-- bad_parity_phase : IN 0 to disable, sets transfer for bad parity assertion
-- 64bit : IN 1 for a 64-bit master, 0 for a 32-bit master
-- quiet : IN 0 to issue error if target reads don't match expected data
-- start_bit : OUT signal passed to simulation master
-- done_bit : IN signal passed from simulation master
-- addr : OUT signal passed to simulation master
-- command : OUT signal passed to simulation master
-- dword_count : OUT signal passed to simulation master
-- initial_data_delay : OUT signal passed to simulation master
-- next_data_delay : OUT signal passed to simulation master
-- bad_parity_phase : OUT signal passed to simulation master
-- m64bit : OUT signal passed to simulation master
-- mquiet : OUT signal passed to simulation master
-- be_array : OUT array passed to simulation master
-- data_array : OUT array passed to simulation master
-- CLK : IN
--
-- NOTE: For multi-quadword transactions, be_array and data_array must be initialized
-- with the appropriate write data for writes, or expected data for reads.
pci_compliance_errors := 0;
address_reg <= target_bar;
data_reg <= x"0000000000000000";
wait_for_clocks(CLK,1);
set_master_abort <= '1';
wait_for_clocks(CLK,1);
set_master_abort <= '0';
wait_for_clocks(CLK,3);
--report "Interrupt Acknowledge Test: Target should NOT respond";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Interrupt Acknowledge Test: Target should NOT respond."));
writeline(output, outline);
pci_access(target_bar,data_reg,INTERRUPT_ACK,x"FF",1,1,1,0,'0','0',
master1_start_bit,master1_done_bit,master1_addr,master1_command,
master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if master_abort = '0' then
--report "... *** Failed ***";
write(outline, string'("... *** Failed ***"));
writeline(output, outline);
pci_compliance_errors := pci_compliance_errors + 1;
else
--report "...Passed";
write(outline, string'("...Passed"));
writeline(output, outline);
end if;
set_master_abort <= '1';
wait_for_clocks(CLK,1);
set_master_abort <= '0';
wait_for_clocks(CLK,4);
--report "Special Cycle Test: Target should NOT respond";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Special Cycle Test: Target should NOT respond."));
writeline(output, outline);
pci_access(target_bar,data_reg,SPECIAL_CYCLE,x"FF",1,1,1,0,'0','0',
master1_start_bit,master1_done_bit,master1_addr,master1_command,
master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if master_abort = '0' then
--report "... *** Failed ***";
write(outline, string'("... *** Failed ***"));
writeline(output, outline);
pci_compliance_errors := pci_compliance_errors + 1;
else
--report "...Passed";
write(outline, string'("...Passed"));
writeline(output, outline);
end if;
address_reg <= x"0000000022001100";
wait_for_clocks(CLK,1);
set_master_abort <= '1';
wait_for_clocks(CLK,1);
set_master_abort <= '0';
wait_for_clocks(CLK,3);
--report "Special Cycle Address Parity Error Test: Target should assert SERRN";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Special Cycle Address Parity Error Test: Target should assert SERRN."));
writeline(output, outline);
pci_access(address_reg,data_reg,SPECIAL_CYCLE,x"FF",1,1,1,1,'0','0',
master1_start_bit,master1_done_bit,master1_addr,master1_command,
master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if serrn_detected = '1' then
--report "...Passed";
write(outline, string'("...Passed"));
writeline(output, outline);
clear_SERR <= '1';
else
--report "... *** Failed ***";
write(outline, string'("... *** Failed ***"));
writeline(output, outline);
pci_compliance_errors := pci_compliance_errors + 1;
end if;
wait_for_clocks(CLK,1);
clear_SERR <= '0';
wait_for_clocks(CLK,4);
--report "Special Cycle Data Parity Error Test: Target should *not* assert SERRN";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Special Cycle Data Parity Error Test: Target should *not* assert SERRN."));
writeline(output, outline);
pci_access(target_bar,data_reg,SPECIAL_CYCLE,x"FF",1,1,1,2,'0','0',
master1_start_bit,master1_done_bit,master1_addr,master1_command,
master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if SERRN_Detected = '1' then
--report "... *** Failed ***";
write(outline, string'("... *** Failed ***"));
writeline(output, outline);
pci_compliance_errors := pci_compliance_errors + 1;
clear_SERR <= '1';
else
--report "...Passed";
write(outline, string'("...Passed"));
writeline(output, outline);
end if;
wait_for_clocks(CLK,1);
clear_SERR <= '0';
wait_for_clocks(CLK,4);
--report "PCI Reserved Command #1 Test: Target should NOT respond";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] PCI Reserved Command #1 Test: Target should NOT respond."));
writeline(output, outline);
pci_access(target_bar,data_reg,CMD_RESERVED_1,x"FF",1,1,1,0,'0','0',
master1_start_bit,master1_done_bit,master1_addr,master1_command,
master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if Master_Abort = '0' then
--report "... *** Failed ***";
write(outline, string'("... *** Failed ***"));
writeline(output, outline);
pci_compliance_errors := pci_compliance_errors + 1;
else
--report "...Passed";
write(outline, string'("...Passed"));
writeline(output, outline);
end if;
wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,3);
--report "PCI Reserved Command #2 Test: Target should NOT respond";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] PCI Reserved Command #2 Test: Target should NOT respond."));
writeline(output, outline);
pci_access(target_bar,data_reg,CMD_RESERVED_2,x"FF",1,1,1,0,'0','0',
master1_start_bit,master1_done_bit,master1_addr,master1_command,
master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if Master_Abort = '0' then
--report "... *** Failed ***";
write(outline, string'("... *** Failed ***"));
writeline(output, outline);
pci_compliance_errors := pci_compliance_errors + 1;
else
--report "...Passed";
write(outline, string'("...Passed"));
writeline(output, outline);
end if;
wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,3);
--report "PCI Reserved Command #3 Test: Target should NOT respond";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] PCI Reserved Command #3 Test: Target should NOT respond."));
writeline(output, outline);
pci_access(target_bar,data_reg,CMD_RESERVED_3,x"FF",1,1,1,0,'0','0',
master1_start_bit,master1_done_bit,master1_addr,master1_command,
master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if Master_Abort = '0' then
--report "... *** Failed ***";
write(outline, string'("... *** Failed ***"));
writeline(output, outline);
pci_compliance_errors := pci_compliance_errors + 1;
else
--report "...Passed";
write(outline, string'("...Passed"));
writeline(output, outline);
end if;
wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,3);
--report "PCI Reserved Command #4 Test: Target should NOT respond";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] PCI Reserved Command #4 Test: Target should NOT respond."));
writeline(output, outline);
pci_access(target_bar,data_reg,CMD_RESERVED_4,x"FF",1,1,1,0,'0','0',
master1_start_bit,master1_done_bit,master1_addr,master1_command,
master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if Master_Abort = '0' then
--report "... *** Failed ***";
write(outline, string'("... *** Failed ***"));
writeline(output, outline);
pci_compliance_errors := pci_compliance_errors + 1;
else
--report "...Passed";
write(outline, string'("...Passed"));
writeline(output, outline);
end if;
address_reg <= x"30000000" & target_bar(31 downto 0);
wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,4);
--report "PCI Dual Address Cycle Test: 32-bit Target should NOT respond";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] PCI Dual Address Cycle Test: 32-bit Target should NOT respond."));
writeline(output, outline);
pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'1','0',
master1_start_bit,master1_done_bit,master1_addr,master1_command,
master1_dword_count,master1_initial_data_delay,master1_next_data_delay,
master1_bad_parity_phase,master1_m64bit,master1_quiet,be_array,data_array,CLK);
if Master_Abort = '0' then
--report "... *** Failed ***";
write(outline, string'("... *** Failed ***"));
writeline(output, outline);
pci_compliance_errors := pci_compliance_errors + 1;
else
--report "...Passed";
write(outline, string'("...Passed"));
writeline(output, outline);
end if;
wait_for_clocks(CLK,1);
set_Master_Abort <= '1';
wait_for_clocks(CLK,1);
set_Master_Abort <= '0';
wait_for_clocks(CLK,3);
--report "PCI Configuration Write and Read Test";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] PCI Configuration Write and Read Test."));
writeline(output, outline);
for i in 0 to 15 loop
data_array(i) <= x"FFFFFFFF";
be_array(i) <= x"F";
end loop;
--report "Config Write Type 0: Target should respond";
write(outline, string'("["));
write(outline, now);
write(outline, string'("] Config Write Type 0: Target should respond."));
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