f128x4_25um.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

-------------------------------------------------------------------------
-- File : f128x4_25um.vhd
-- Date : Jan. 14, 1998
-- Authors : Ed Bezeg, Brian Faith, John Birkner, Brian Small, Mike Dini
-- Creation Date: Mon May 06 13:42:48 2002
-- Created By SpDE Version: SpDE 9.3 Alpha Build3
-- Copyright (C) 1998, Customers of QuickLogic may copy and modify this
-- file for use in designing QuickLogic devices only.
-- Description : This file is autogenerated RTL code that describes the
-- control logic to implement a FIFO using QuickLogic's RAM resources.
-------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

   -- inputs: =din[3:0]=,pop,push,clk,rst
   -- outputs: =dout[3:0]=,emptyn,fulln

entity f128x4_25um is
   port (pop : in std_logic;
         push : in std_logic;
         clk : in std_logic;
         rst : in std_logic;
         emptyn : out std_logic;
         fulln : out std_logic;
         din : in std_logic_vector (3 downto 0);
         dout : out std_logic_vector (3 downto 0));
end f128x4_25um;

architecture arch of f128x4_25um is
signal wr_enable : std_logic;
signal rd_enable : std_logic;
signal emptyn_reg : std_logic;
signal fulln_reg : std_logic;
signal init_read : std_logic;
signal rd_status_enable : std_logic;
signal wr_addr : std_logic_vector (6 downto 0);
signal rd_addr : std_logic_vector (6 downto 0);
signal status_addr : std_logic_vector (6 downto 0);


-- Declare the components
component ucnt7_25um
   port (rst, enable, clk : in std_logic; 
         q : out std_logic_vector (6 downto 0));
end component ;

component r128x4_25um
    port (we, re, wclk, rclk : in std_logic;
          wa, ra : in std_logic_vector (6 downto 0);
          wd : in std_logic_vector (3 downto 0);
          rd : out std_logic_vector (3 downto 0));
end component;

component updcnt7_25um
   port (rst, up, down, clk : in std_logic;
         q : out std_logic_vector (6 downto 0));
end component;

begin --arch

-- Generate enable lines for the address counters 
wr_enable <= (push and fulln_reg) after 1 ns;  -- If push command and FIFO is not full
rd_enable <= (pop and emptyn_reg) or init_read after 1 ns; -- If pop command and FIFO is not empty 
rd_status_enable <= (pop and emptyn_reg) after 1 ns;
fulln <= fulln_reg after 1 ns;
emptyn <= emptyn_reg after 1 ns;

-- Instantiate the counters for the addresses 
wr_counter : ucnt7_25um 
   port map (rst => rst, enable => wr_enable, clk => clk, q => wr_addr);
rd_counter : ucnt7_25um 
   port map (rst => rst, enable => rd_enable, clk => clk, q => rd_addr);

-- Instantiate the RAM block for FIFO 
ram : r128x4_25um 
   port map (wa => wr_addr, ra => rd_addr, wd => din, rd => dout, 
             we => wr_enable, re => rd_enable, wclk => clk, rclk => clk);

-- Instantiate the Up Down counter for keeping track of empty or full
updcnt : updcnt7_25um 
   port map (rst => rst, up => wr_enable, down => rd_status_enable,
             clk => clk, q => status_addr);

-- Check for positive edge of system clock 
main : process (clk, rst)
begin
   if rst = '1' then
      init_read <= '1' after 1 ns;
      fulln_reg <= '1' after 1 ns;
      emptyn_reg <= '0' after 1 ns;
   else
      if Rising_Edge(clk) then
         -- clear the init_read on the first clock after a reset 
         -- init_read is needed to sychronize the RAM read address on reset
         init_read <= '0' after 1 ns;
         -- calculate fulln flag
         if (((status_addr = "1111111") and (push = '1') and (pop = '0')) or 
           ((fulln_reg = '0') and (pop = '0')) ) then
            fulln_reg <= '0' after 1 ns;
         else 
            fulln_reg <= '1' after 1 ns;
         end if;
         -- calculate empty flag
         if (((status_addr = "0000001") and (pop = '1') and (push = '0')) or 
        ((emptyn_reg = '0') and (push = '0') )) then 
            emptyn_reg <= '0' after 1 ns;
         else
            emptyn_reg <= '1' after 1 ns;
         end if;
      end if;
   end if;
end process main;
end arch;