r128x4_25um.tb

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

------------------------------------------------------------------------
-- File : r128x4_25um.tb
-- Design Date: June 9, 1998
-- Creation Date : Mon May 06 13:42:48 2002

-- Created By SpDE Version : SpDE 9.3 Alpha Build3
-- Author: Robert Maul, QuickLogic Corporation,
-- Copyright (C) 1998, Customers of QuickLogic may copy and modify this
-- file for use in designing QuickLogic devices only.
-- Description: This is a sample test bench for your RAM bank.
-- For each address, data is loaded in then read back
-- The data is the address of the RAM location.
-- The intended use of this file is to help users verify that the
-- RAM Bank that is generated by SpDE is functionally correct.
------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity test_r128x4_25um is
end test_r128x4_25um;

architecture behave of test_r128x4_25um is

component r128x4_25um
   port (WE,RE,WCLK,RCLK : in std_logic;
         WA, RA : in std_logic_vector (6 downto 0);
         WD : in std_logic_vector (3 downto 0);
         RD : out std_logic_vector (3 downto 0));
end component;

signal GND : std_logic;
signal WA, RA : std_logic_vector (6 downto 0);
signal WE,RE,WCLK,RCLK : std_logic;
signal WD : std_logic_vector (3 downto 0);
signal RD : std_logic_vector (3 downto 0);
signal address  : std_logic_vector (6 downto 0);
signal stopClock : boolean;

constant period: time := 40 ns;

begin -- ram is loaded with data and then, as it is unloaded, a
      -- check is performed to see if the same data is read back.
   GND <= '0';
   m : r128x4_25um
      port map (wa  => wa,
                ra  => ra,
                wd => wd,
                rd  => rd,
                re => re,
                rclk  => rclk,
                we  => we,
                wclk  => wclk);

   WClockGenerator: process
   begin
      while not stopClock loop
         wclk <= '0';
         wait for period/2;
         wclk <= '1';
         wait for period/2;
      end loop;
   end process WClockGenerator;

   RClockGenerator: process
   begin
      while not stopClock loop
         rclk <= '0';
         wait for period/2;
         rclk <= '1';
         wait for period/2;
      end loop;
   end process RClockGenerator;

   Stimulus: process
      variable data  : std_logic_vector (3 downto 0);
      variable address  : std_logic_vector (6 downto 0);
   begin
      stopClock <= FALSE;
      we <= '1';
      re <= '1';
      data := "0000";
      address := "0000000";
      for L in 1 to 128 loop
         wa <= address;
         wd <= data;
         wait for period;
         data := data + 1;
         address := address + 1;
      end loop;
      data := "0000";
      wait for period;
      we <= '0';
      address := "0000000";
      for L in 1 to 128 loop
         ra <= address;
         wait for period;
         address := address + 1;
      end loop;
      stopClock <= TRUE;
   end process Stimulus;

end behave;

configuration behave_test_r128x4_25um of test_r128x4_25um is
for behave
end for;
end behave_test_r128x4_25um;