cardbus_5632.qdf

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

  gate I_137.dataout_1_i[27] master Q_AND2I1 end
  gate DMA.Usr_RdData_1[27] master Q_MUX2X0 end
  gate DMA.Usr_RdData[27] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[26] master Q_MUX2X3 end
  gate I_137.G_100 master Q_OR2I0 end
  gate I_137.G_112 master Q_MUX2X3 end
  gate I_137.dataout_1_0_iv_i[26] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[26] master Q_MUX2X0 end
  gate DMA.Usr_RdData[26] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[25] master Q_MUX2X3 end
  gate I_137.G_111 master Q_MUX2X3 end
  gate I_137.dataout_1_0_iv_i[25] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[25] master Q_MUX2X0 end
  gate DMA.Usr_RdData[25] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[24] master Q_MUX2X3 end
  gate I_137.G_110 master Q_MUX2X3 end
  gate I_137.dataout_1_0_iv_i[24] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[24] master Q_MUX2X0 end
  gate DMA.Usr_RdData[24] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[23] master Q_MUX2X3 end
  gate I_137.dataout_1_i[23] master Q_AND2I1 end
  gate DMA.Usr_RdData_1[23] master Q_MUX2X0 end
  gate DMA.Usr_RdData[23] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[22] master Q_MUX2X3 end
  gate I_137.G_92 master Q_XOR2I0 end
  gate I_137.dataout_1[22] master Q_MUX2X3 end
  gate DMA.Usr_RdData_1[22] master Q_MUX2X1 end
  gate DMA.Usr_RdData[22] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[21] master Q_MUX2X3 end
  gate I_137.dataout_1[21] master Q_MUX2X3 end
  gate DMA.Usr_RdData_1[21] master Q_MUX2X1 end
  gate DMA.Usr_RdData[21] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[20] master Q_MUX2X3 end
  gate I_137.dataout_1[20] master Q_MUX2X3 end
  gate DMA.Usr_RdData_1[20] master Q_MUX2X1 end
  gate DMA.Usr_RdData[20] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[19] master Q_MUX2X3 end
  gate I_137.dataout_1_1[19] master Q_MUX2X3 end
  gate I_137.dataout_1_i[19] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[19] master Q_MUX2X0 end
  gate DMA.Usr_RdData[19] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[18] master Q_MUX2X3 end
  gate I_137.dataout_1_1[18] master Q_MUX2X0 end
  gate I_137.dataout_1[18] master Q_MUX2X3 end
  gate DMA.Usr_RdData_1[18] master Q_MUX2X1 end
  gate DMA.Usr_RdData[18] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[17] master Q_MUX2X3 end
  gate I_137.dataout_1_1[17] master Q_MUX2X0 end
  gate I_137.dataout_1[17] master Q_MUX2X3 end
  gate DMA.Usr_RdData_1[17] master Q_MUX2X1 end
  gate DMA.Usr_RdData[17] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[16] master Q_MUX2X3 end
  gate I_137.dataout_1_1[16] master Q_MUX2X0 end
  gate I_137.dataout_1[16] master Q_MUX2X3 end
  gate DMA.Usr_RdData_1[16] master Q_MUX2X1 end
  gate DMA.Usr_RdData[16] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[15] master Q_MUX2X3 end
  gate I_137.dataout_1_1[15] master Q_MUX2X3 end
  gate I_137.dataout_1_i[15] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[15] master Q_MUX2X0 end
  gate DMA.Usr_RdData[15] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[14] master Q_MUX2X3 end
  gate I_137.dataout_1_1[14] master Q_MUX2X3 end
  gate I_137.dataout_1_i[14] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[14] master Q_MUX2X0 end
  gate DMA.Usr_RdData[14] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[13] master Q_MUX2X3 end
  gate I_137.dataout_1_1[13] master Q_MUX2X3 end
  gate I_137.dataout_1_i[13] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[13] master Q_MUX2X0 end
  gate DMA.Usr_RdData[13] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[12] master Q_MUX2X3 end
  gate I_137.dataout_1_1[12] master Q_MUX2X3 end
  gate I_137.dataout_1_i[12] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[12] master Q_MUX2X0 end
  gate DMA.Usr_RdData[12] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[11] master Q_MUX2X3 end
  gate I_137.dataout_1_1[11] master Q_MUX2X3 end
  gate I_137.dataout_1_i[11] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[11] master Q_MUX2X0 end
  gate DMA.Usr_RdData[11] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[10] master Q_MUX2X3 end
  gate I_137.dataout_1_1[10] master Q_MUX2X3 end
  gate I_137.dataout_1_i[10] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[10] master Q_MUX2X0 end
  gate DMA.Usr_RdData[10] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[9] master Q_MUX2X3 end
  gate I_137.dataout_1_1[9] master Q_MUX2X3 end
  gate I_137.dataout_1_i[9] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[9] master Q_MUX2X0 end
  gate DMA.Usr_RdData[9] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[8] master Q_MUX2X3 end
  gate I_137.dataout_1_1[8] master Q_MUX2X0 end
  gate I_137.dataout_1[8] master Q_MUX2X3 end
  gate DMA.Usr_RdData_1[8] master Q_MUX2X1 end
  gate DMA.Usr_RdData[8] master Q_MUX2X2 end
  gate I_137.dataout_1_1[7] master Q_MUX2X3 end
  gate I_137.dataout_1[7] master Q_MUX2X1 end
  gate DMA.Usr_RdData_1[7] master Q_MUX2X3 end
  gate DMA.Usr_RdData[7] master Q_MUX2X1 end
  gate I_137.dataout_1_1[6] master Q_MUX2X3 end
  gate I_137.dataout_1[6] master Q_MUX2X1 end
  gate DMA.Usr_RdData_1[6] master Q_MUX2X3 end
  gate DMA.Usr_RdData[6] master Q_MUX2X1 end
  gate I_137.dataout_1_1[5] master Q_MUX2X3 end
  gate I_137.dataout_1[5] master Q_MUX2X1 end
  gate DMA.Usr_RdData_1[5] master Q_MUX2X3 end
  gate DMA.Usr_RdData[5] master Q_MUX2X1 end
  gate I_137.dataout_1_1[4] master Q_MUX2X3 end
  gate I_137.dataout_1[4] master Q_MUX2X1 end
  gate DMA.Usr_RdData_1[4] master Q_MUX2X3 end
  gate DMA.Usr_RdData[4] master Q_MUX2X1 end
  gate I_137.dataout_1_1[3] master Q_MUX2X3 end
  gate I_137.dataout_1[3] master Q_MUX2X1 end
  gate DMA.Usr_RdData_1[3] master Q_MUX2X3 end
  gate DMA.Usr_RdData[3] master Q_MUX2X1 end
  gate I_137.dataout_1_0[2] master Q_MUX2X3 end
  gate I_137.dataout_1_1[2] master Q_MUX2X0 end
  gate I_137.dataout_1[2] master Q_MUX2X2 end
  gate DMA.Usr_RdData_1[2] master Q_MUX2X3 end
  gate DMA.Usr_RdData[2] master Q_MUX2X1 end
  gate I_137.dataout_1_0[1] master Q_MUX2X3 end
  gate I_137.dataout_1_1[1] master Q_MUX2X0 end
  gate I_137.dataout_1[1] master Q_MUX2X2 end
  gate DMA.Usr_RdData_1[1] master Q_MUX2X3 end
  gate DMA.Usr_RdData[1] master Q_MUX2X1 end
  gate I_137.dataout_1_0[0] master Q_MUX2X3 end
  gate I_137.dataout_1_1[0] master Q_MUX2X0 end
  gate I_137.dataout_1[0] master Q_MUX2X2 end
  gate DMA.Usr_RdData_1[0] master Q_MUX2X3 end
  gate DMA.Usr_RdData[0] master Q_MUX2X1 end
  gate I222.CCLKRUN_n_oe_0_and2 master Q_AND2I0 end
  gate I222.un4_cint_n_i_0 master Q_OR2I1 end
  gate I222.CSTSCHG_0_and2_2 master Q_AND3I0 end
  gate I222.CSTSCHG_0_and2_1 master Q_AND3I0 end
  gate I222.CSTSCHG_0_and2_0 master Q_AND3I0 end
  gate I222.G_97 master Q_OR2I0 end
  gate I222.CSTSCHG_0_and2_99 master Q_AND2I0 end
  gate I222.CSTSCHG_0_and2 master Q_AND3I0 end
  gate I222.CSTSCHG_0 master Q_OR4I0 end
  gate I222.CAUDIO_0 master Q_MUX2X3 end
  gate I222.G_90 master Q_XNOR2I0 end
  gate I222.CAUDIO_1_and2 master Q_AND2I2 end
  gate DMA.G_322 master Q_MUX2X0 end
  gate I249.un3_bar5_hit_int_0.N_325_i master Q_XNOR2I0 end
  gate I249.un3_bar5_hit_int_0.N_324_i master Q_XOR2I0 end
  gate I249.un3_bar5_hit_int_0.N_358_i master Q_XOR2I0 end
  gate I249.un3_bar5_hit_int_0.I_364 master Q_XOR2I0 end
  gate I249.un3_bar5_hit_int_0.I_32_155 master Q_AND4I3 end
  gate I249.un3_bar5_hit_int_0.N_61_i master Q_XOR2I0 end
  gate I249.un3_bar5_hit_int_0.I_58 master Q_XOR2I0 end
  gate I249.un3_bar5_hit_int_0.I_32_150 master Q_AND2I2 end
  gate I249.un3_bar5_hit_int_0.N_94_i master Q_XOR2I0 end
  gate I249.un3_bar5_hit_int_0.I_92 master Q_XOR2I0 end
  gate I249.un3_bar5_hit_int_0.I_32_149 master Q_AND2I2 end
  gate I249.un3_bar5_hit_int_0.N_127_i master Q_XNOR2I0 end
  gate I249.un3_bar5_hit_int_0.N_126_i master Q_XOR2I0 end
  gate I249.un3_bar5_hit_int_0.N_160_i master Q_XOR2I0 end
  gate I249.un3_bar5_hit_int_0.N_159_i master Q_XOR2I0 end
  gate I249.un3_bar5_hit_int_0.I_32_158 master Q_AND6I3 end
  gate I249.un3_bar5_hit_int_0.N_193_i master Q_XOR2I0 end
  gate I249.un3_bar5_hit_int_0.I_194 master Q_XOR2I0 end
  gate I249.un3_bar5_hit_int_0.I_32_146 master Q_AND2I2 end
  gate I249.un3_bar5_hit_int_0.N_226_i master Q_XOR2I0 end
  gate I249.un3_bar5_hit_int_0.I_228 master Q_XOR2I0 end
  gate I249.un3_bar5_hit_int_0.I_32_145 master Q_AND2I2 end
  gate I249.un3_bar5_hit_int_0.N_259_i master Q_XNOR2I0 end
  gate I249.un3_bar5_hit_int_0.N_258_i master Q_XOR2I0 end
  gate I249.un3_bar5_hit_int_0.N_292_i master Q_XOR2I0 end
  gate I249.un3_bar5_hit_int_0.N_291_i master Q_XOR2I0 end
  gate I249.un3_bar5_hit_int_0.I_32_157 master Q_AND6I3 end
  gate I249.un3_bar5_hit_int_0.N_391_i master Q_XOR2I0 end
  gate I249.un3_bar5_hit_int_0.N_390_i master Q_XOR2I0 end
  gate I249.un3_bar5_hit_int_0.I_32 master Q_AND5I2 end
  gate I250.un2_last_cycle_0 master Q_OR2I0 end
  gate I250.CIS_Hit_0 master Q_MUX2X0 end
  gate DMA.un2_usr_write_0_and2 master Q_AND2I0 end
  gate DMA.wrdmacnt_239 master Q_AND3I0 end
  gate DMA.ldrdcnt master Q_AND2I0 end
  gate DMA.ldwrcnt master Q_AND2I0 end
  gate DMA.dec_bcnt_1_0_0_and2_0 master Q_AND2I0 end
  gate DMA.dec_bcnt_1_0_0 master Q_OR2I0 end
  gate DMA.G_277 master Q_AND2I2 end
  gate DMA.un1_dmasm_3_0_0_and2 master Q_AND2I0 end
  gate DMA.G_291 master Q_OR2I1 end
  gate DMA.G_297 master Q_OR2I1 end
  gate DMA.N_523_i master Q_AND2I2 end
  gate DMA.G_312 master Q_OR3I1 end
  gate DMA.un1_un49_dmasm_5_0_0_and2 master Q_AND4I1 end
  gate DMA.un1_un49_dmasm_5_0_0 master Q_OR2I0 end
  gate DMA.G_272 master Q_AND2I0 end
  gate DMA.G_89_0_and2_241 master Q_AND2I0 end
  gate DMA.G_89_0_and2 master Q_AND3I0 end
  gate DMA.mst_wrbe_6[2] master Q_MUX2X0 end
  gate DMA.mst_wrbe_6[3] master Q_MUX2X0 end
  gate DMA.un1_un26_wrctrl_1_i_0_and2_0_2 master Q_AND2I0 end
  gate DMA.un1_un26_wrctrl_1_i_0_and2_0 master Q_AND3I0 end
  gate DMA.mst_wrbe_7[0] master Q_MUX2X0 end
  gate DMA.mst_wrbe_7[1] master Q_MUX2X0 end
  gate DMA.G_317 master Q_OR2I0 end
  gate DMA.un1_dmasm_3_0_0_and2_0 master Q_AND2I1 end
  gate DMA.G_301 master Q_AND2I2 end
  gate DMA.G_302 master Q_OR2I1 end
  gate DMA.un1_un66_dmasm_2_0_0_and2 master Q_AND2I1 end
  gate DMA.un1_un118_dmasm_3_0_0 master Q_OR2I0 end
  gate DMA.un1_un118_dmasm_4_0_0_and2_0 master Q_OR3I3 end
  gate DMA.un1_un118_dmasm_4_0_0_and2_1 master Q_AND3I0 end
  gate DMA.un1_un118_dmasm_4_0_0_and2 master Q_AND2I0 end
  gate DMA.un1_un118_dmasm_4_0_0 master Q_OR5I1 end
  gate DMA.un1_un99_dmasm_2_0_0_and2 master Q_AND3I1 end
  gate DMA.un1_un99_dmasm_2_0_0_and2_0 master Q_AND3I1 end
  gate DMA.un1_un99_dmasm_2_0_0 master Q_OR2I0 end
  gate DMA.mst_rdbe_load_done_3_iv_0_0_and2 master Q_AND2I0 end
  gate DMA.G_290 master Q_AND2I1 end
  gate DMA.un1_un66_dmasm_2_0_and2_0_2_66 master Q_AND2I2 end
  gate DMA.mst_rdbe_load_done_3_iv_0_0_and2_0 master Q_AND3I0 end
  gate DMA.mst_rdbe_load_done_3_iv_0_0 master Q_AND2I2 end
  gate DMA.mst_rdbe_load_done_0 master Q_MUX2X2 end
  gate DMA.un2_mst_tabort_det master Q_OR2I0 end
  gate DMA.un1_un26_wrctrl_1_i_0_and2 master Q_AND2I0 end
  gate DMA.G_267 master Q_AND3I0 end
  gate DMA.dmawren_local_4_i_0_or2 master Q_OR2I0 end
  gate DMA.un1_wrcnt0_3_i_0 master Q_OR2I0 end
  gate DMA.DMAWrEn_0 master Q_MUX2X0 end
  gate DMA.un1_un10_wrctrl_1_i_or2_0_and2 master Q_AND2I0 end
  gate DMA.G_271 master Q_AND2I0 end
  gate DMA.dmarden_local_4_i_0_or2 master Q_OR2I0 end
  gate DMA.un1_rdcnt0_3_i_0_and2 master Q_AND3I0 end
  gate DMA.un1_rdcnt0_3_i_0 master Q_OR2I0 end
  gate DMA.DMARdEn_0 master Q_MUX2X0 end
  gate DMA.un1_un66_dmasm_2_0_0_and2_0_114 master Q_AND3I0 end
  gate DMA.un1_un66_dmasm_2_0_0_and2_0 master Q_AND3I0 end
  gate DMA.un1_un66_dmasm_2_0_0 master Q_AND2I2 end
  gate DMA.un1_dmasm_4_i_0_and2 master Q_AND2I0 end
  gate DMA.un1_dmasm_4_i_0 master Q_OR2I0 end
  gate DMA.Mst_WrData_Valid_0 master Q_MUX2X0 end
  gate DMA.dmawrerr_3_i_and2_i master Q_AND2I2 end
  gate DMA.un1_un26_wrctrl_1_i_0 master Q_OR2I0 end
  gate DMA.dmawrerr_0 master Q_MUX2X2 end
  gate DMA.dmarderr_3_i_and2_i master Q_AND2I2 end
  gate DMA.un1_un10_wrctrl_1_i_or2_0 master Q_OR2I0 end
  gate DMA.dmarderr_0 master Q_MUX2X2 end
  gate DMA.mst_rdcmd_0[0] master Q_MUX2X0 end
  gate DMA.mst_rdcmd_0[1] master Q_MUX2X0 end
  gate DMA.mst_rdcmd_0[2] master Q_MUX2X0 end
  gate DMA.mst_rdcmd_0[3] master Q_MUX2X0 end
  gate DMA.mst_rdbe_0[0] master Q_MUX2X0 end
  gate DMA.mst_rdbe_0[1] master Q_MUX2X0 end
  gate DMA.mst_rdbe_0[2] master Q_MUX2X0 end
  gate DMA.mst_rdbe_0[3] master Q_MUX2X0 end
  gate DMA.mst_wrcmd_0[0] master Q_MUX2X0 end
  gate DMA.mst_wrcmd_0[1] master Q_MUX2X0 end
  gate DMA.mst_wrcmd_0[2] master Q_MUX2X0 end
  gate DMA.mst_wrdata_sel_0 master Q_MUX2X0 end
  gate DMA.mst_wrbe_sel_0 master Q_MUX2X0 end
  gate DMA.mst_rddata_sel_0 master Q_MUX2X0 end
  gate DMA.mst_rdbe_sel_0 master Q_MUX2X0 end
  gate DMA.Mst_Rd_Term_Sel_0 master Q_MUX2X0 end
  gate DMA.Mst_LatCntEn_0 master Q_MUX2X0 end
  gate DMA.LocalEn_0 master Q_MUX2X0 end
  gate DMA.un2_mst_rddata_valid_0_and2 master Q_AND2I0 end
  gate DMA.wrdreg_230 master Q_AND3I0 end
  gate DMA.wrdreg master Q_AND3I0 end
  gate DMA.un5_mst_rddata_valid master Q_OR2I0 end
  gate DMA.WD_Reg_0[0] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[1] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[2] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[3] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[4] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[5] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[6] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[7] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[8] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[9] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[10] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[11] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[12] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[13] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[14] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[15] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[16] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[17] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[18] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[19] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[20] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[21] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[22] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[23] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[24] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[25] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[26] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[27] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[28] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[29] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[30] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[31] master Q_MUX2X0 end
  gate DMA.un1_dmasm_3_0_0 master Q_AND3I3 end
  gate DMA.Mst_Burst_Req_0 master Q_MUX2X1 end
  gate DMA.ldrdadrcnt_3 master Q_AND2I0 end
  gate DMA.ldwradrcnt master Q_AND3I0 end
  gate DMA.WrAdrReg.q_local_4[0] master Q_MUX2X0 end
  gate DMA.WrAdrReg.q_local_4[1] master Q_MUX2X0 end
  gate DMA.WrAdrReg.q_local_4[2] master Q_MUX2X0 end
  gate DMA.WrAdrReg.q_local_4[3] master Q_MUX2X0 end
  gate DMA.WrAdrReg.q_local_4[4] master Q_MUX2X0 end
  gate DMA.WrAdrReg.q_local_4[5] master Q_MUX2X0 end
  gate DMA.WrAdrReg.q_local_4[6] master Q_MUX2X0 end
  gate DMA.WrAdrReg.q_local_4[7] master Q_MUX2X0 end
  gate DMA.WrAdrReg.q_local_4[8] master Q_MUX2X0 end
  gate DMA.WrAdrReg.q_local_4[9] master Q_MUX2X0 end
  gate DMA.WrAdrReg.q_local_4[10] master Q_MU