cardbus_5632.qdf

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

  gate I_137.un1_perfcount_1.CO14 master Q_AND2 end
  gate I_137.un1_perfcount_1.CO16 master Q_AND2 end
  gate I_137.un1_perfcount_1.CO17 master Q_AND2 end
  gate I_137.un1_perfcount_1.SUM0 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM1 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM2 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM3 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM4 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM5 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM6 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM7 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM8 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM9 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM10 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM11 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM12 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM13 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM14 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM15 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM16 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM17 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM18 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM19 master Q_INCX end
  gate I_137.un1_stopcount_1.CO1 master Q_AND2 end
  gate I_137.un1_stopcount_1.SUM0 master Q_INCX end
  gate I_137.un1_stopcount_1.SUM1 master Q_INCX end
  gate I_137.un1_stopcount_1.SUM2 master Q_INCX end
  gate WrBuff.I_120 master DFFPA end
  gate WrBuff.I_45 master Q_OR2I0 end
  gate WrBuff.I_50 master Q_AND2I1 end
  gate WrBuff.I_69 master Q_AND2I1 end
  gate WrBuff.I_17.I_11 master Q_AND3I1 end
  gate WrBuff.I_17.I_12 master Q_XOR2I0 end
  gate WrBuff.I_17.I_10.I_2 master LOGIC2 end
  gate WrBuff.I_17.I_9.I_2 master LOGIC2 end
  gate WrBuff.I_18.I_11 master Q_AND3I1 end
  gate WrBuff.I_18.I_12 master Q_XOR2I0 end
  gate WrBuff.I_18.I_10.I_2 master LOGIC2 end
  gate WrBuff.I_18.I_9.I_2 master LOGIC2 end
  gate WrBuff.I_85.I_11 master Q_AND3I1 end
  gate WrBuff.I_85.I_12 master Q_XOR2I0 end
  gate WrBuff.I_85.I_10.I_2 master LOGIC2 end
  gate WrBuff.I_85.I_9.I_2 master LOGIC2 end
  gate WrBuff.I_19.I_11 master Q_AND3I1 end
  gate WrBuff.I_19.I_12 master Q_XOR2I0 end
  gate WrBuff.I_19.I_10.I_2 master LOGIC2 end
  gate WrBuff.I_19.I_9.I_2 master LOGIC2 end
  gate WrBuff.I_26.I_11 master Q_AND3I1 end
  gate WrBuff.I_26.I_12 master Q_XOR2I0 end
  gate WrBuff.I_26.I_10.I_2 master LOGIC2 end
  gate WrBuff.I_26.I_9.I_2 master LOGIC2 end
  gate WrBuff.I136.I26 master Q_OR2I0 end
  gate WrBuff.I136.I23 master Q_AND3I3 end
  gate WrBuff.I136.I15 master Q_AND2I2 end
  gate WrBuff.I136.I16 master Q_MUX2X2 end
  gate WrBuff.I136.I17 master Q_MUX2X2 end
  gate WrBuff.I136.I19 master Q_AND2I0 end
  gate WrBuff.I136.I24 master Q_AND2I0 end
  gate WrBuff.I136.I20 master Q_AND2I0 end
  gate WrBuff.I136.I21 master DFFPC end
  gate WrBuff.I136.I22 master DFFPC end
  gate WrBuff.I136.I25 master DFF end
  gate WrBuff.I136.I13 master DFF end
  gate WrBuff.I135.I26 master Q_OR2I0 end
  gate WrBuff.I135.I23 master Q_AND3I3 end
  gate WrBuff.I135.I15 master Q_AND2I2 end
  gate WrBuff.I135.I16 master Q_MUX2X2 end
  gate WrBuff.I135.I17 master Q_MUX2X2 end
  gate WrBuff.I135.I19 master Q_AND2I0 end
  gate WrBuff.I135.I24 master Q_AND2I0 end
  gate WrBuff.I135.I20 master Q_AND2I0 end
  gate WrBuff.I135.I21 master DFFPC end
  gate WrBuff.I135.I22 master DFFPC end
  gate WrBuff.I135.I25 master DFF end
  gate WrBuff.I135.I13 master DFF end
  gate WrBuff.I137.r128x32_25umI1 master RAM128X18_25UM end
  gate WrBuff.I137.r128x32_25umI2 master RAM128X18_25UM end
  gate Rdbuff.I_120 master DFFPA end
  gate Rdbuff.I_45 master Q_OR2I0 end
  gate Rdbuff.I_69 master Q_AND2I1 end
  gate Rdbuff.I_17.I_11 master Q_AND3I1 end
  gate Rdbuff.I_17.I_12 master Q_XOR2I0 end
  gate Rdbuff.I_17.I_10.I_2 master LOGIC2 end
  gate Rdbuff.I_17.I_9.I_2 master LOGIC2 end
  gate Rdbuff.I_18.I_11 master Q_AND3I1 end
  gate Rdbuff.I_18.I_12 master Q_XOR2I0 end
  gate Rdbuff.I_18.I_10.I_2 master LOGIC2 end
  gate Rdbuff.I_18.I_9.I_2 master LOGIC2 end
  gate Rdbuff.I_85.I_11 master Q_AND3I1 end
  gate Rdbuff.I_85.I_12 master Q_XOR2I0 end
  gate Rdbuff.I_85.I_10.I_2 master LOGIC2 end
  gate Rdbuff.I_85.I_9.I_2 master LOGIC2 end
  gate Rdbuff.I_19.I_11 master Q_AND3I1 end
  gate Rdbuff.I_19.I_12 master Q_XOR2I0 end
  gate Rdbuff.I_19.I_10.I_2 master LOGIC2 end
  gate Rdbuff.I_19.I_9.I_2 master LOGIC2 end
  gate Rdbuff.I_26.I_11 master Q_AND3I1 end
  gate Rdbuff.I_26.I_12 master Q_XOR2I0 end
  gate Rdbuff.I_26.I_10.I_2 master LOGIC2 end
  gate Rdbuff.I_26.I_9.I_2 master LOGIC2 end
  gate Rdbuff.I136.I26 master Q_OR2I0 end
  gate Rdbuff.I136.I23 master Q_AND3I3 end
  gate Rdbuff.I136.I15 master Q_AND2I2 end
  gate Rdbuff.I136.I16 master Q_MUX2X2 end
  gate Rdbuff.I136.I17 master Q_MUX2X2 end
  gate Rdbuff.I136.I19 master Q_AND2I0 end
  gate Rdbuff.I136.I24 master Q_AND2I0 end
  gate Rdbuff.I136.I20 master Q_AND2I0 end
  gate Rdbuff.I136.I21 master DFFPC end
  gate Rdbuff.I136.I22 master DFFPC end
  gate Rdbuff.I136.I25 master DFF end
  gate Rdbuff.I136.I13 master DFF end
  gate Rdbuff.I135.I26 master Q_OR2I0 end
  gate Rdbuff.I135.I23 master Q_AND3I3 end
  gate Rdbuff.I135.I15 master Q_AND2I2 end
  gate Rdbuff.I135.I16 master Q_MUX2X2 end
  gate Rdbuff.I135.I17 master Q_MUX2X2 end
  gate Rdbuff.I135.I24 master Q_AND2I0 end
  gate Rdbuff.I135.I21 master DFFPC end
  gate Rdbuff.I135.I22 master DFFPC end
  gate Rdbuff.I135.I25 master DFF end
  gate Rdbuff.I135.I13 master DFF end
  gate Rdbuff.I137.r128x32_25umI1 master RAM128X18_25UM end
  gate Rdbuff.I137.r128x32_25umI2 master RAM128X18_25UM end
  gate I249.un19_usraddr_local_1.CO6 master Q_INCSKIP2 pack end
  gate I249.un19_usraddr_local_1.CO1 master Q_AND2 end
  gate I249.un19_usraddr_local_1.CO2 master Q_AND2 end
  gate I249.un19_usraddr_local_1.CO4 master Q_AND2 end
  gate I249.un19_usraddr_local_1.CO5 master Q_AND2 end
  gate I249.un19_usraddr_local_1.SUM1 master Q_INCX end
  gate I249.un19_usraddr_local_1.SUM2 master Q_INCX end
  gate I249.un19_usraddr_local_1.SUM3 master Q_INCX end
  gate I249.un19_usraddr_local_1.SUM4 master Q_INCX end
  gate I249.un19_usraddr_local_1.SUM5 master Q_INCX end
  gate I249.un19_usraddr_local_1.SUM6 master Q_INCX end
  gate I249.un19_usraddr_local_1.SUM7 master Q_INCX end
  gate I251.ram.r128x4_25umI1 master RAM128X18_25UM end
  gate I251.wr_counter.main.q_reg_3_1.CO3 master Q_INCSKIP pack end
  gate I251.wr_counter.main.q_reg_3_1.CO1 master Q_AND2 end
  gate I251.wr_counter.main.q_reg_3_1.CO2 master Q_AND2 end
  gate I251.wr_counter.main.q_reg_3_1.CO4 master Q_AND2 end
  gate I251.wr_counter.main.q_reg_3_1.CO5 master Q_AND2 end
  gate I251.wr_counter.main.q_reg_3_1.SUM0 master Q_INCX end
  gate I251.wr_counter.main.q_reg_3_1.SUM1 master Q_INCX end
  gate I251.wr_counter.main.q_reg_3_1.SUM2 master Q_INCX end
  gate I251.wr_counter.main.q_reg_3_1.SUM3 master Q_INCX end
  gate I251.wr_counter.main.q_reg_3_1.SUM4 master Q_INCX end
  gate I251.wr_counter.main.q_reg_3_1.SUM5 master Q_INCX end
  gate I251.wr_counter.main.q_reg_3_1.SUM6 master Q_INCX end
  gate I251.rd_counter.main.q_reg_3_1.CO3 master Q_INCSKIP pack end
  gate I251.rd_counter.main.q_reg_3_1.CO1 master Q_AND2 end
  gate I251.rd_counter.main.q_reg_3_1.CO2 master Q_AND2 end
  gate I251.rd_counter.main.q_reg_3_1.CO4 master Q_AND2 end
  gate I251.rd_counter.main.q_reg_3_1.CO5 master Q_AND2 end
  gate I251.rd_counter.main.q_reg_3_1.SUM0 master Q_INCX end
  gate I251.rd_counter.main.q_reg_3_1.SUM1 master Q_INCX end
  gate I251.rd_counter.main.q_reg_3_1.SUM2 master Q_INCX end
  gate I251.rd_counter.main.q_reg_3_1.SUM3 master Q_INCX end
  gate I251.rd_counter.main.q_reg_3_1.SUM4 master Q_INCX end
  gate I251.rd_counter.main.q_reg_3_1.SUM5 master Q_INCX end
  gate I251.rd_counter.main.q_reg_3_1.SUM6 master Q_INCX end
  gate I251.G_17.I_2 master LOGIC2 end
  gate I251.G_17.I_7 master LOGIC2 end
  gate I251.G_17.I_12 master LOGIC2 end
  gate I251.G_17.I_17 master LOGIC2 end
  gate I251.G_17.I_22 master LOGIC2 end
  gate I251.G_17.I_27 master LOGIC2 end
  gate I251.G_17.I_32 master LOGIC2 end
  gate I251.G_17.I_42 master LOGIC2 end
  gate I251.G_17.I_47 master LOGIC2 end
  gate I251.G_17.I_62 master LOGIC2 end
  gate I251.G_17.I_67 master LOGIC2 end
  gate I251.G_17.I_72 master LOGIC2 end
  gate I251.G_17.I_77 master LOGIC2 end
  gate I251.G_17.I_82 master LOGIC2 end
  gate I251.G_17.I_87 master LOGIC2 end
  gate I251.G_17.I_92 master LOGIC2 end
  gate I249.G_302 master Q_AND3I0 end
  gate I249.G_305 master Q_OR2I0 end
  gate I249.G_304 master Q_OR3I0 end
  gate I249.G_306 master Q_OR2I0 end
  gate I249.G_156 master Q_AND3I0 end
  gate I249.cfgdata_1_iv_0_and2_0[1] master Q_AND2I0 end
  gate I249.cfgdata_1_iv_0[1] master Q_OR2I0 end
  gate I249.cfgdata_0_iv_0_and2[2] master Q_AND2I0 end
  gate I249.G_295 master Q_AND2I1 end
  gate I249.cfgdata_0_iv_0_and2_0[2] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0[2] master Q_OR2I0 end
  gate I249.cfgdata_0_iv_0_and2[3] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0_and2_0[3] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0[3] master Q_OR2I0 end
  gate I249.cfgdata_0_iv_0_and2[4] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0_and2_0[4] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0[4] master Q_OR2I0 end
  gate I249.cfgdata_1_iv_0_and2[5] master Q_AND2I0 end
  gate I249.cfgdata_1_iv_0[5] master Q_OR2I0 end
  gate I249.cfgdata_1_iv_0_and2[6] master Q_AND2I0 end
  gate I249.cfgdata_1_iv_0_and2_0[6] master Q_AND2I0 end
  gate I249.cfgdata_1_iv_0[6] master Q_OR3I0 end
  gate I249.cfgdata_1_iv_0_and2[7] master Q_AND2I0 end
  gate I249.cfgdata_1_iv_0[7] master Q_OR2I0 end
  gate I249.cfgdata_1_iv_0_and2[8] master Q_AND2I0 end
  gate I249.cfgdata_1_iv_0_and2_0[8] master Q_AND2I0 end
  gate I249.cfgdata_1_iv_0[8] master Q_OR3I0 end
  gate I249.cfgdata_0_and2[9] master Q_AND2I0 end
  gate I249.G_297 master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0_and2_0[10] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0_and2_1[10] master Q_AND2I0 end
  gate I249.G_310 master Q_OR2I0 end
  gate I249.cfgdata_0_iv_0[10] master Q_OR3I0 end
  gate I249.bar0_reg_m[11] master Q_AND2I0 end
  gate I249.LatTimerReg_m[3] master Q_AND2I0 end
  gate I249.cfgdata_0_iv[11] master Q_OR3I0 end
  gate I249.cfgdata_1_iv_0_and2_0[12] master Q_AND2I0 end
  gate I249.cfgdata_1_iv_0_and2_1[12] master Q_AND2I0 end
  gate I249.cfgdata_1_iv_0[12] master Q_OR4I0 end
  gate I249.cfgdata_0_iv_0_and2_0[13] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0_and2_1[13] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0[13] master Q_OR3I0 end
  gate I249.bar0_reg_m[14] master Q_AND2I0 end
  gate I249.LatTimerReg_m[6] master Q_AND2I0 end
  gate I249.cfgdata_0_iv[14] master Q_OR3I0 end
  gate I249.cfgdata_0_iv_0_and2_0[15] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0_and2_1[15] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0[15] master Q_OR3I0 end
  gate I249.cfgdata_0_iv_0_and2_0[16] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0[16] master Q_OR2I0 end
  gate I249.cfgdata_1_iv_0_and2[17] master Q_AND2I0 end
  gate I249.cfgdata_1_iv_0[17] master Q_OR3I0 end
  gate I249.cfgdata_0_iv_0_and2_0[18] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0[18] master Q_OR3I0 end
  gate I249.cfgdata_1_iv_0_and2_1[19] master Q_AND2I0 end
  gate I249.cfgdata_1_iv_0[19] master Q_OR4I0 end
  gate I249.cfgdata_0_iv_0_and2_0[20] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0[20] master Q_OR3I0 end
  gate I249.cfgdata_0_iv_0_and2_0[21] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0[21] master Q_OR2I0 end
  gate I249.cfgdata_0_iv_0_and2_0[22] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0[22] master Q_OR2I0 end
  gate I249.cfgdata_0_iv_0_and2_0[23] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0[23] master Q_OR3I0 end
  gate I249.cfgdata_0_iv_0_and2_0[24] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0_and2[24] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0[24] master Q_OR4I0 end
  gate I249.cfgdata_0_iv_0_and2[25] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0[25] master Q_OR4I0 end
  gate I249.cfgdata_0_iv_0_and2[26] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0[26] master Q_OR3I0 end
  gate I249.cfgdata_0_iv_0_and2_1[27] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0[27] master Q_OR3I0 end
  gate I249.cfgdata_1_iv_0_and2_0[28] master Q_OR2I2 end
  gate I249.cfgdata_1_iv_0_and2[28] master Q_AND2I0 end
  gate I249.cfgdata_1_iv_0[28] master Q_OR5I1 end
  gate I249.cfgdata_0_iv_0_and2_1[29] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0_and2_0[29] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0[29] master Q_OR4I0 end
  gate I249.cfgdata_0_iv_0_and2_0[30] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0_and2[30] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0[30] master Q_OR4I0 end
  gate I249.cfgdata_0_iv_0_and2_1[31] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0_and2_0[31] master Q_AND2I0 end
  gate I249.cfgdata_0_iv_0[31] master Q_OR4I0 end
  gate I249.G_321 master Q_OR2I0 end
  gate I249.un4_usr_wrcmd_0_and2 master Q_AND3I0 end
  gate DMA.Mst_BE_0[0] master Q_MUX2X3 end
  gate DMA.G_294 master Q_OR2I0 end
  gate DMA.Mst_BE[0] master Q_MUX2X1 end
  gate DMA.Mst_BE_0[1] master Q_MUX2X3 end
  gate DMA.Mst_BE[1] master Q_MUX2X1 end
  gate DMA.Mst_BE_0[2] master Q_MUX2X3 end
  gate DMA.Mst_BE[2] master Q_MUX2X1 end
  gate DMA.Mst_BE_0[3] master Q_MUX2X3 end
  gate DMA.Mst_BE[3] master Q_MUX2X1 end
  gate DMA.G_321 master Q_MUX2X0 end
  gate DMA.un1_bcnt_eq_2_2_i master Q_AND2I2 end
  gate DMA.G_174 master Q_OR5I1 end
  gate DMA.Mst_One_Read_0_0 master Q_OR2I0 end
  gate DMA.Mst_Two_Reads_0_0 master Q_OR2I0 end
  gate DMA.G_295 master Q_OR2I0 end
  gate DMA.G_311 master Q_XOR2I0 end
  gate DMA.pci_cmd_1_iv_0_0_mux2[1] master Q_MUX2X2 end
  gate DMA.pci_cmd_1_iv_0_0_and2_1[1] master Q_AND3I1 end
  gate DMA.pci_cmd_1_iv_0_0[1] master Q_OR4I0 end
  gate DMA.G_320 master Q_MUX2X0 end
  gate DMA.pci_cmd_0_iv_0_0_and2_1[2] master Q_AND2I0 end
  gate DMA.pci_cmd_0_iv_0_0[2] master Q_OR4I1 end
  gate DMA.mstwrad_sel6_226 master Q_AND2I0 end
  gate DMA.mstwrad_sel6 master Q_AND3I0 end
  gate I_137.Usr_Rdy_0_and2 master Q_AND2I0 end
  gate I_137.Usr_Rdy_0_and2_0 master Q_AND4I3 end
  gate I_137.Usr_Rdy_0 master Q_OR2I0 end
  gate I222.cstschg_regs_out_0_i_and2[7] master Q_AND2I0 end
  gate DMA.Usr_RdData_0[31] master Q_MUX2X3 end
  gate I_137.G_98_198 master Q_OR3I0 end
  gate I_137.dataout_1_i[31] master Q_AND2I1 end
  gate DMA.Usr_RdData_sn.G_23_0_and2 master Q_AND3I0 end
  gate DMA.Usr_RdData_1[31] master Q_MUX2X0 end
  gate DMA.Usr_RdData[31] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[30] master Q_MUX2X3 end
  gate I_137.dataout_1_i[30] master Q_AND2I1 end
  gate DMA.Usr_RdData_1[30] master Q_MUX2X0 end
  gate DMA.Usr_RdData[30] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[29] master Q_MUX2X3 end
  gate I_137.dataout_1_i[29] master Q_AND2I1 end
  gate DMA.Usr_RdData_1[29] master Q_MUX2X0 end
  gate DMA.Usr_RdData[29] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[28] master Q_MUX2X3 end
  gate I_137.dataout_1_i[28] master Q_AND2I1 end
  gate DMA.Usr_RdData_1[28] master Q_MUX2X0 end
  gate DMA.Usr_RdData[28] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[27] master Q_MUX2X3 end