📄 cardbus_5632.qdf
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gate ladpadsQ28Q master BIPADIFF_25UM end
gate ladpadsQ27Q master BIPADIFF_25UM end
gate ladpadsQ26Q master BIPADIFF_25UM end
gate ladpadsQ25Q master BIPADIFF_25UM end
gate ladpadsQ24Q master BIPADIFF_25UM end
gate ladpadsQ23Q master BIPADIFF_25UM end
gate ladpadsQ22Q master BIPADIFF_25UM end
gate ladpadsQ21Q master BIPADIFF_25UM end
gate ladpadsQ20Q master BIPADIFF_25UM end
gate ladpadsQ19Q master BIPADIFF_25UM end
gate ladpadsQ18Q master BIPADIFF_25UM end
gate ladpadsQ17Q master BIPADIFF_25UM end
gate ladpadsQ16Q master BIPADIFF_25UM end
gate ladpadsQ15Q master BIPADIFF_25UM end
gate ladpadsQ14Q master BIPADIFF_25UM end
gate ladpadsQ13Q master BIPADIFF_25UM end
gate ladpadsQ12Q master BIPADIFF_25UM end
gate ladpadsQ11Q master BIPADIFF_25UM end
gate ladpadsQ10Q master BIPADIFF_25UM end
gate ladpadsQ9Q master BIPADIFF_25UM end
gate ladpadsQ8Q master BIPADIFF_25UM end
gate ladpadsQ7Q master BIPADIFF_25UM end
gate ladpadsQ6Q master BIPADIFF_25UM end
gate ladpadsQ5Q master BIPADIFF_25UM end
gate ladpadsQ4Q master BIPADIFF_25UM end
gate ladpadsQ3Q master BIPADIFF_25UM end
gate ladpadsQ2Q master BIPADIFF_25UM end
gate ladpadsQ1Q master BIPADIFF_25UM end
gate ladpadsQ0Q master BIPADIFF_25UM end
gate I189 master CKPAD_25UM end
gate I241 master OUTPAD_25UM end
gate I242 master OUTPAD_25UM end
gate I243 master OUTPAD_25UM end
gate I230 master OUTPAD_25UM end
gate I231 master OUTPAD_25UM end
gate I232 master OUTPAD_25UM end
gate CIS_ADRQ9Q master OUTPAD_25UM end
gate CIS_ADRQ8Q master OUTPAD_25UM end
gate CIS_ADRQ7Q master OUTPAD_25UM end
gate CIS_ADRQ6Q master OUTPAD_25UM end
gate CIS_ADRQ5Q master OUTPAD_25UM end
gate CIS_ADRQ4Q master OUTPAD_25UM end
gate CIS_ADRQ3Q master OUTPAD_25UM end
gate CIS_ADRQ2Q master OUTPAD_25UM end
gate I217 master OUTPAD_25UM end
gate ledpadsQ7Q master OUTPAD_25UM end
gate ledpadsQ6Q master OUTPAD_25UM end
gate ledpadsQ5Q master OUTPAD_25UM end
gate ledpadsQ4Q master OUTPAD_25UM end
gate ledpadsQ3Q master OUTPAD_25UM end
gate ledpadsQ2Q master OUTPAD_25UM end
gate ledpadsQ1Q master OUTPAD_25UM end
gate ledpadsQ0Q master OUTPAD_25UM end
gate I201 master OUTPAD_25UM end
gate I202 master OUTPAD_25UM end
gate I203 master OUTPAD_25UM end
gate I204 master OUTPAD_25UM end
gate I205 master INPADFF_25UM end
gate I207 master INPADFF_25UM end
gate I208 master INPADFF_25UM end
gate I209 master INPADFF_25UM end
gate I166 master DFF end
gate I159 master Q_AND4I3 end
gate I160 master DFFE end
gate I157 master Q_AND3I1 end
gate I153 master Q_OR3I0 end
gate I154 master Q_AND2I1 end
gate I158 master Q_AND2I1 end
gate I163 master Q_AND2I0 end
gate I161 master Q_OR2I0 end
gate Mst_WrData_MuxQ31Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ30Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ29Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ28Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ27Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ26Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ25Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ24Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ23Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ22Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ21Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ20Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ19Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ18Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ17Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ16Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ15Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ14Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ13Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ12Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ11Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ10Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ9Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ8Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ7Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ6Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ5Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ4Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ3Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ2Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ1Q master Q_MUX2X0 end
gate Mst_WrData_MuxQ0Q master Q_MUX2X0 end
gate mxledQ7Q master Q_MUX2X0 end
gate mxledQ6Q master Q_MUX2X0 end
gate mxledQ5Q master Q_MUX2X0 end
gate mxledQ4Q master Q_MUX2X0 end
gate mxledQ3Q master Q_MUX2X0 end
gate mxledQ2Q master Q_MUX2X0 end
gate mxledQ1Q master Q_MUX2X0 end
gate mxledQ0Q master Q_MUX2X0 end
gate I_124 master DFFP end
gate I149 master DFFP end
gate I218 master Q_INV end
gate I_129 master Q_INV end
gate ledinvQ7Q master Q_INV end
gate ledinvQ6Q master Q_INV end
gate ledinvQ5Q master Q_INV end
gate ledinvQ4Q master Q_INV end
gate ledinvQ3Q master Q_INV end
gate ledinvQ2Q master Q_INV end
gate ledinvQ1Q master Q_INV end
gate ledinvQ0Q master Q_INV end
gate I212 master Q_INV end
gate I213 master Q_INV end
gate DMA.BRSTCNTR2.I6.QL4 master DNFXBIT end
gate DMA.BRSTCNTR2.I6.QL3 master DNFXBIT end
gate DMA.BRSTCNTR2.I6.QL2 master DNFXBIT end
gate DMA.BRSTCNTR2.I6.QL1 master DNFXBIT end
gate DMA.BRSTCNTR2.I3.QL5 master Q_AND5I4 end
gate DMA.BRSTCNTR2.I3.QL4 master DNFXBIT end
gate DMA.BRSTCNTR2.I3.QL3 master DNFXBIT end
gate DMA.BRSTCNTR2.I3.QL2 master DNFXBIT end
gate DMA.BRSTCNTR2.I3.QL1 master DNFXBIT end
gate DMA.BRSTCNTR.I6.QL4 master DNFXBIT end
gate DMA.BRSTCNTR.I6.QL3 master DNFXBIT end
gate DMA.BRSTCNTR.I6.QL2 master DNFXBIT end
gate DMA.BRSTCNTR.I6.QL1 master DNFXBIT end
gate DMA.BRSTCNTR.I3.QL5 master Q_AND5I4 end
gate DMA.BRSTCNTR.I3.QL4 master DNFXBIT end
gate DMA.BRSTCNTR.I3.QL3 master DNFXBIT end
gate DMA.BRSTCNTR.I3.QL2 master DNFXBIT end
gate DMA.BRSTCNTR.I3.QL1 master DNFXBIT end
gate DMA.WrCntReg.I4.QL4 master DNFXBIT end
gate DMA.WrCntReg.I4.QL3 master DNFXBIT end
gate DMA.WrCntReg.I4.QL2 master DNFXBIT end
gate DMA.WrCntReg.I4.QL1 master DNFXBIT end
gate DMA.WrCntReg.I3.QL5 master Q_AND5I4 end
gate DMA.WrCntReg.I3.QL4 master DNFXBIT end
gate DMA.WrCntReg.I3.QL3 master DNFXBIT end
gate DMA.WrCntReg.I3.QL2 master DNFXBIT end
gate DMA.WrCntReg.I3.QL1 master DNFXBIT end
gate DMA.WrCntReg.I2.QL5 master Q_AND5I4 end
gate DMA.WrCntReg.I2.QL4 master DNFXBIT end
gate DMA.WrCntReg.I2.QL3 master DNFXBIT end
gate DMA.WrCntReg.I2.QL2 master DNFXBIT end
gate DMA.WrCntReg.I2.QL1 master DNFXBIT end
gate DMA.WrCntReg.I1.QL5 master Q_AND5I4 end
gate DMA.WrCntReg.I1.QL4 master DNFXBIT end
gate DMA.WrCntReg.I1.QL3 master DNFXBIT end
gate DMA.WrCntReg.I1.QL2 master DNFXBIT end
gate DMA.WrCntReg.I1.QL1 master DNFXBIT end
gate DMA.RdCntReg.I4.QL4 master DNFXBIT end
gate DMA.RdCntReg.I4.QL3 master DNFXBIT end
gate DMA.RdCntReg.I4.QL2 master DNFXBIT end
gate DMA.RdCntReg.I4.QL1 master DNFXBIT end
gate DMA.RdCntReg.I3.QL5 master Q_AND5I4 end
gate DMA.RdCntReg.I3.QL4 master DNFXBIT end
gate DMA.RdCntReg.I3.QL3 master DNFXBIT end
gate DMA.RdCntReg.I3.QL2 master DNFXBIT end
gate DMA.RdCntReg.I3.QL1 master DNFXBIT end
gate DMA.RdCntReg.I2.QL5 master Q_AND5I4 end
gate DMA.RdCntReg.I2.QL4 master DNFXBIT end
gate DMA.RdCntReg.I2.QL3 master DNFXBIT end
gate DMA.RdCntReg.I2.QL2 master DNFXBIT end
gate DMA.RdCntReg.I2.QL1 master DNFXBIT end
gate DMA.RdCntReg.I1.QL5 master Q_AND5I4 end
gate DMA.RdCntReg.I1.QL4 master DNFXBIT end
gate DMA.RdCntReg.I1.QL3 master DNFXBIT end
gate DMA.RdCntReg.I1.QL2 master DNFXBIT end
gate DMA.RdCntReg.I1.QL1 master DNFXBIT end
gate DMA.WrAdrReg.un1_q_local_1.CO6 master Q_INCSKIP2 pack end
gate DMA.WrAdrReg.un1_q_local_1.CO12 master Q_INCSKIP2 pack end
gate DMA.WrAdrReg.un1_q_local_1.CO18 master Q_INCSKIP2 pack end
gate DMA.WrAdrReg.un1_q_local_1.CO24 master Q_INCSKIP2 pack end
gate DMA.WrAdrReg.un1_q_local_1.CO27 master Q_INCSKIP pack end
gate DMA.WrAdrReg.un1_q_local_1.CO1 master Q_AND2 end
gate DMA.WrAdrReg.un1_q_local_1.CO2 master Q_AND2 end
gate DMA.WrAdrReg.un1_q_local_1.CO4 master Q_AND2 end
gate DMA.WrAdrReg.un1_q_local_1.CO5 master Q_AND2 end
gate DMA.WrAdrReg.un1_q_local_1.CO7 master Q_AND2 end
gate DMA.WrAdrReg.un1_q_local_1.CO8 master Q_AND2 end
gate DMA.WrAdrReg.un1_q_local_1.CO10 master Q_AND2 end
gate DMA.WrAdrReg.un1_q_local_1.CO11 master Q_AND2 end
gate DMA.WrAdrReg.un1_q_local_1.CO13 master Q_AND2 end
gate DMA.WrAdrReg.un1_q_local_1.CO14 master Q_AND2 end
gate DMA.WrAdrReg.un1_q_local_1.CO16 master Q_AND2 end
gate DMA.WrAdrReg.un1_q_local_1.CO17 master Q_AND2 end
gate DMA.WrAdrReg.un1_q_local_1.CO19 master Q_AND2 end
gate DMA.WrAdrReg.un1_q_local_1.CO20 master Q_AND2 end
gate DMA.WrAdrReg.un1_q_local_1.CO22 master Q_AND2 end
gate DMA.WrAdrReg.un1_q_local_1.CO23 master Q_AND2 end
gate DMA.WrAdrReg.un1_q_local_1.CO25 master Q_AND2 end
gate DMA.WrAdrReg.un1_q_local_1.CO26 master Q_AND2 end
gate DMA.WrAdrReg.un1_q_local_1.CO28 master Q_AND2 end
gate DMA.WrAdrReg.un1_q_local_1.SUM0 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM1 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM2 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM3 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM4 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM5 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM6 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM7 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM8 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM9 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM10 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM11 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM12 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM13 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM14 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM15 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM16 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM17 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM18 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM19 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM20 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM21 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM22 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM23 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM24 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM25 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM26 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM27 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM28 master Q_INCX end
gate DMA.WrAdrReg.un1_q_local_1.SUM29 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.CO6 master Q_INCSKIP2 pack end
gate DMA.RdAdrReg.un1_q_local_1.CO12 master Q_INCSKIP2 pack end
gate DMA.RdAdrReg.un1_q_local_1.CO18 master Q_INCSKIP2 pack end
gate DMA.RdAdrReg.un1_q_local_1.CO24 master Q_INCSKIP2 pack end
gate DMA.RdAdrReg.un1_q_local_1.CO27 master Q_INCSKIP pack end
gate DMA.RdAdrReg.un1_q_local_1.CO1 master Q_AND2 end
gate DMA.RdAdrReg.un1_q_local_1.CO2 master Q_AND2 end
gate DMA.RdAdrReg.un1_q_local_1.CO4 master Q_AND2 end
gate DMA.RdAdrReg.un1_q_local_1.CO5 master Q_AND2 end
gate DMA.RdAdrReg.un1_q_local_1.CO7 master Q_AND2 end
gate DMA.RdAdrReg.un1_q_local_1.CO8 master Q_AND2 end
gate DMA.RdAdrReg.un1_q_local_1.CO10 master Q_AND2 end
gate DMA.RdAdrReg.un1_q_local_1.CO11 master Q_AND2 end
gate DMA.RdAdrReg.un1_q_local_1.CO13 master Q_AND2 end
gate DMA.RdAdrReg.un1_q_local_1.CO14 master Q_AND2 end
gate DMA.RdAdrReg.un1_q_local_1.CO16 master Q_AND2 end
gate DMA.RdAdrReg.un1_q_local_1.CO17 master Q_AND2 end
gate DMA.RdAdrReg.un1_q_local_1.CO19 master Q_AND2 end
gate DMA.RdAdrReg.un1_q_local_1.CO20 master Q_AND2 end
gate DMA.RdAdrReg.un1_q_local_1.CO22 master Q_AND2 end
gate DMA.RdAdrReg.un1_q_local_1.CO23 master Q_AND2 end
gate DMA.RdAdrReg.un1_q_local_1.CO25 master Q_AND2 end
gate DMA.RdAdrReg.un1_q_local_1.CO26 master Q_AND2 end
gate DMA.RdAdrReg.un1_q_local_1.CO28 master Q_AND2 end
gate DMA.RdAdrReg.un1_q_local_1.SUM0 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM1 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM2 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM3 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM4 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM5 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM6 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM7 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM8 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM9 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM10 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM11 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM12 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM13 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM14 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM15 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM16 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM17 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM18 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM19 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM20 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM21 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM22 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM23 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM24 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM25 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM26 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM27 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM28 master Q_INCX end
gate DMA.RdAdrReg.un1_q_local_1.SUM29 master Q_INCX end
gate I_137.target_ram3.r128a8I1 master RAM128X9 end
gate I_137.target_ram2.r128a8I1 master RAM128X9 end
gate I_137.target_ram1.r128a8I1 master RAM128X9 end
gate I_137.target_ram0.r128a8I1 master RAM128X9 end
gate I_137.I_6 master Q_DECX end
gate I_137.I_7 master Q_DECX end
gate I_137.I_8 master Q_DECX end
gate I_137.un1_waitcount_1.CO1 master Q_AND2 end
gate I_137.un1_waitcount_1.SUM0 master Q_INCX end
gate I_137.un1_waitcount_1.SUM1 master Q_INCX end
gate I_137.un1_waitcount_1.SUM2 master Q_INCX end
gate I_137.un1_perfcount_1.CO6 master Q_INCSKIP2 pack end
gate I_137.un1_perfcount_1.CO12 master Q_INCSKIP2 pack end
gate I_137.un1_perfcount_1.CO18 master Q_INCSKIP2 pack end
gate I_137.un1_perfcount_1.CO1 master Q_AND2 end
gate I_137.un1_perfcount_1.CO2 master Q_AND2 end
gate I_137.un1_perfcount_1.CO4 master Q_AND2 end
gate I_137.un1_perfcount_1.CO5 master Q_AND2 end
gate I_137.un1_perfcount_1.CO7 master Q_AND2 end
gate I_137.un1_perfcount_1.CO8 master Q_AND2 end
gate I_137.un1_perfcount_1.CO10 master Q_AND2 end
gate I_137.un1_perfcount_1.CO11 master Q_AND2 end
gate I_137.un1_perfcount_1.CO13 master Q_AND2 end
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