📄 cardbus_wrapper_test.tb
字号:
if (tb_CAUDIO = '0') then
write(outline, string'("CAUDIO Test #2 - Passed..."));
writeline(output, outline);
j := j + 1;
end if;
--enable only BAM, check CAUDIO
-- write to mask offset, enable bit 5, BAM
tb_BAM <= '1';
tb_PWM <= '0';
data_reg <= x"FFFFFFFF00000020";
pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
master1_quiet,be_array,data_array,CLK);
for i in 1 to 2 loop
wait until (CLK'event and CLK='1');
end loop;
if (tb_CAUDIO = '1') then
write(outline, string'("CAUDIO Test #3a - Passed..."));
writeline(output, outline);
j := j + 1;
end if;
tb_BAM <= '0';
tb_PWM <= '1';
for i in 1 to 2 loop
wait until (CLK'event and CLK='1');
end loop;
if (tb_CAUDIO = '0') then
write(outline, string'("CAUDIO Test #3b - Passed..."));
writeline(output, outline);
j := j + 1;
end if;
--enable only PWM, check CAUDIO
-- write to mask offset, enable bit 6, PWM
data_reg <= x"FFFFFFFF00000040";
pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
master1_quiet,be_array,data_array,CLK);
for i in 1 to 2 loop
wait until (CLK'event and CLK='1');
end loop;
if (tb_CAUDIO = '1') then
write(outline, string'("CAUDIO Test #4a - Passed..."));
writeline(output, outline);
j := j + 1;
end if;
tb_BAM <= '1';
tb_PWM <= '0';
for i in 1 to 2 loop
wait until (CLK'event and CLK='1');
end loop;
if (tb_CAUDIO = '0') then
write(outline, string'("CAUDIO Test #4b - Passed..."));
writeline(output, outline);
j := j + 1;
end if;
write(outline, string'("["));
write(outline, now);
write(outline, string'("] END OF CAUDIO TEST - "));
write(outline, integer'image(j));
write(outline, string'(" out of 6 tests passed."));
writeline(output, outline);
passed <= j;
end caudio_test;
procedure cclkrun_test (
signal address_reg : inout std_logic_vector(63 downto 0);
signal data_reg : inout std_logic_vector(63 downto 0);
signal target_bar : inout std_logic_vector(63 downto 0);
signal master_abort : in std_logic;
signal set_master_abort : out std_logic;
signal serrn_detected : in std_logic;
signal perrn_detected : in std_logic;
signal clear_serr : out std_logic;
signal clear_disconnect : out std_logic;
signal disconnect_detected : in std_logic;
signal clear_perr : out std_logic;
SIGNAL master1_start_bit : OUT std_logic;
SIGNAL master1_done_bit : IN std_logic;
SIGNAL master1_addr : OUT std_logic_vector(63 downto 0);
SIGNAL master1_command : OUT std_logic_vector(3 downto 0);
SIGNAL master1_dword_count : OUT integer;
SIGNAL master1_initial_data_delay : OUT integer;
SIGNAL master1_next_data_delay : OUT integer;
SIGNAL master1_bad_parity_phase: OUT integer;
SIGNAL master1_m64bit : OUT std_logic;
SIGNAL master1_quiet : OUT std_logic;
SIGNAL be_array : OUT BYTE_ARRAY_TYPE;
SIGNAL data_array : OUT DATA_ARRAY_TYPE;
SIGNAL CLK : IN std_logic;
signal tb_CCLKRUN_n : inout std_logic;
signal tb_clk_resume : out std_logic;
signal tb_clk_stopped : in std_logic;
signal passed : out integer
) is
begin
j := 0;
write(outline, string'("["));
write(outline, now);
write(outline, string'("] START OF CCLKRUN_N TEST"));
writeline(output, outline);
-- signal stop clock
-- resume request after stopped, check CCLKRUN, supply clock
-- signal stop clock
-- resume request before stopped, check CCLKRUN, supply clock
-- make sure the clock is still running
if tb_clk_stopped = '0' then
write(outline, string'("CCLKRUN_N Test #1 - Passed..."));
writeline(output, outline);
j := j + 1;
end if;
-- signal stop clock
-- clk_cnt = 0 --> 1
wait until (CLK'event and CLK = '1');
tb_CCLKRUN_n <= '1';
wait until (CLK'event and CLK = '1');
-- need to shift and interleave the tests and the actual set up of values
-- clk_cnt = 1 --> 0
tb_CCLKRUN_n <= '0';
wait until (CLK'event and CLK = '1');
if tb_clk_stopped = '0' then
write(outline, string'("CCLKRUN_N Test #2 - Passed..."));
writeline(output, outline);
j := j + 1;
end if;
-- clk_cnt =0 --> 1
tb_CCLKRUN_n <= '1';
wait until (CLK'event and CLK = '1');
if tb_clk_stopped = '0' then
write(outline, string'("CCLKRUN_N Test #3 - Passed..."));
writeline(output, outline);
j := j + 1;
end if;
-- clk_cnt = 1 --> 2 (tb_CCLKRUN_n = '1')
-- wait until (CLK'event and CLK = '1');
for i in 1 to 4 loop
wait until (CLK'event and CLK='1');
end loop;
-- clk_cnt = 2
tb_CCLKRUN_n <= 'H';
wait until (CLK'event and CLK = '1');
if tb_clk_stopped = '1' then
write(outline, string'("CCLKRUN_N Test #4 - Passed..."));
writeline(output, outline);
j := j + 1;
end if;
-- clk resume for one clock cycle
-- same as tb_cclkrun_n <= 1'0;
-- clk_cnt =2 --> 3
tb_clk_resume <= '1';
wait until (CLK'event and CLK = '1');
if tb_clk_stopped = '1' then
write(outline, string'("CCLKRUN_N Test #5 - Passed..."));
writeline(output, outline);
j := j + 1;
end if;
-- clk_cnt = 3 --> 2
tb_clk_resume <= '0';
-- so set up for the next state and then check the current test case
wait until (CLK'event and CLK = '1');
if tb_clk_stopped = '1' then
write(outline, string'("CCLKRUN_N Test #6 - Passed..."));
writeline(output, outline);
j := j + 1;
end if;
-- clk_cnt = 2 --> 3
tb_clk_resume <= '1';
wait until (CLK'event and CLK = '1');
if tb_clk_stopped = '1' then
write(outline, string'("CCLKRUN_N Test #7 - Passed..."));
writeline(output, outline);
j := j + 1;
end if;
-- clk_cnt = 3 --> 0
tb_clk_resume <= '1';
-- so set up for the next state and then check the current test case
wait until (CLK'event and CLK = '1');
if tb_clk_stopped = '1' then
write(outline, string'("CCLKRUN_N Test #8 - Passed..."));
writeline(output, outline);
j := j + 1;
end if;
-- clk resume for two clock cycles to resume the clock
-- clk_cnt =3 --> 0
tb_clk_resume <= '0';
tb_cclkrun_n <= '0';
wait until (CLK'event and CLK = '1');
if tb_clk_stopped = '0' then
write(outline, string'("CCLKRUN_N Test #9 - Passed..."));
writeline(output, outline);
j := j + 1;
end if;
write(outline, string'("["));
write(outline, now);
write(outline, string'("] END OF CCLKRUN_N TEST - "));
write(outline, integer'image(j));
write(outline, string'(" out of 9 tests passed."));
writeline(output, outline);
passed <= j;
end cclkrun_test;
procedure cis_readback_test (
signal address_reg : inout std_logic_vector(63 downto 0);
signal data_reg : inout std_logic_vector(63 downto 0);
signal target_bar : inout std_logic_vector(63 downto 0);
signal master_abort : in std_logic;
signal set_master_abort : out std_logic;
signal serrn_detected : in std_logic;
signal perrn_detected : in std_logic;
signal clear_serr : out std_logic;
signal clear_disconnect : out std_logic;
signal disconnect_detected : in std_logic;
signal clear_perr : out std_logic;
SIGNAL master1_start_bit : OUT std_logic;
SIGNAL master1_done_bit : IN std_logic;
SIGNAL master1_addr : OUT std_logic_vector(63 downto 0);
SIGNAL master1_command : OUT std_logic_vector(3 downto 0);
SIGNAL master1_dword_count : OUT integer;
SIGNAL master1_initial_data_delay : OUT integer;
SIGNAL master1_next_data_delay : OUT integer;
SIGNAL master1_bad_parity_phase: OUT integer;
SIGNAL master1_m64bit : OUT std_logic;
SIGNAL master1_quiet : OUT std_logic;
SIGNAL be_array : OUT BYTE_ARRAY_TYPE;
SIGNAL data_array : OUT DATA_ARRAY_TYPE;
SIGNAL CLK : IN std_logic;
signal passed : out integer
) is
begin
j := 0;
write(outline, string'("["));
write(outline, now);
write(outline, string'("] START OF CIS Read Back TEST"));
writeline(output, outline);
-- clear event notice
address_reg <= CardBus_Bar;
-- address_reg <= x"00000000FFBE0000";
data_reg <= x"FFFFFFFFFFFFFFFF";
be_array(0) <= "1111";
be_array(1) <= "1111";
be_array(2) <= "1111";
be_array(3) <= "1111";
data_array(0) <= x"04030201";
data_array(1) <= x"08070605";
data_array(2) <= x"0C0B0A09";
data_array(3) <= x"100F0E0D";
pci_access(address_reg,data_reg,MEM_READ,x"FF",4,1,1,0,'0','0',
master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
master1_quiet,be_array,data_array,CLK);
write(outline, string'("["));
write(outline, now);
write(outline, string'("] END OF CIS Read Back TEST - "));
writeline(output, outline);
j := j + 1;
passed <= j;
end cis_readback_test;
end package body cardbus_wrapper_test_package;⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -