cardbus_wrapper_test.tb

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

                      SIGNAL master1_done_bit : IN std_logic;
                      SIGNAL master1_addr : OUT std_logic_vector(63 downto 0);
                      SIGNAL master1_command : OUT std_logic_vector(3 downto 0);
                      SIGNAL master1_dword_count : OUT integer;
                      SIGNAL master1_initial_data_delay : OUT integer;
                      SIGNAL master1_next_data_delay : OUT integer;
                      SIGNAL master1_bad_parity_phase: OUT integer;
                      SIGNAL master1_m64bit : OUT std_logic;
                      SIGNAL master1_quiet : OUT std_logic;
                      SIGNAL be_array : OUT BYTE_ARRAY_TYPE;
                      SIGNAL data_array : OUT DATA_ARRAY_TYPE;
					  SIGNAL CLK : IN std_logic;
   					  signal tb_intr: out std_logic;
				      signal tb_CINT_n   : in std_logic;
				      signal passed   : out integer
   					  ) is
begin

	j := 0;
	write(outline, string'("["));
	write(outline, now);
	write(outline, string'("] START OF CINT TEST"));
	writeline(output, outline);

	-- ctu notes -------
	--Test CardBus Interrupt Events (4)
	--Test 1: Enable Intr, set intr_ps high, CINT_n should be asserted
	--Test 2: Enable Intr, force intr function event high, CINT_n should be asserted
	--Test 3: Disable Intr, set intr_ps high, CINT_n should NOT be asserted
	--Test 4: Disable Intr, force intr function event high, CINT_n should NOT be asserted
	------- 

	-- clear event notice
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFFFFFFFFFF";


	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);
	-- all fields should be  clear

	-- write to mask offset, enable INTR and disable all others
	-- the INTR bit is the 15th bit
	address_reg <= FcnMaskReg_Addr;
	data_reg <= x"0000000000008000";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	tb_intr <= '1';

	-- present state - intr bit should also be 1
	address_reg <= FcnStateReg_Addr;
	data_reg <= x"0000000000008000";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- check if event function register has been set
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"0000000000000000";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	if (tb_CINT_n = '0') then
		write(outline, string'("CINT_N Test #1 - Passed..."));
		writeline(output, outline);
		j := j + 1;
	end if;

	tb_intr <= '0';

	-- clear event notice
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFFFFFFFFFF";


	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	--enable INTR, force intr requests, check interrupt
	address_reg <= FcnForceReg_Addr;
	data_reg <= x"0000000000008000";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- present state - intr bit should also be 1
	address_reg <= FcnStateReg_Addr;
	data_reg <= x"0000000000000000";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- check if event function register has been set
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"0000000000008000";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	if (tb_CINT_n = '0') then
		write(outline, string'("CINT_N Test #2 - Passed..."));
		writeline(output, outline);
		j := j + 1;
	end if;

	-- clear event notice
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFFFFFFFFFF";


	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- write to mask offset, disable everything
	address_reg <= FcnMaskReg_Addr;
	data_reg <= x"0000000000000000";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	tb_intr <= '1';

	-- present state - intr bit should also be 1
	address_reg <= FcnStateReg_Addr;
	data_reg <= x"0000000000008000";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- check if function event register has been set
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"0000000000000000";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	if (tb_CINT_n = '1') then
		write(outline, string'("CINT_N Test #3 - Passed..."));
		writeline(output, outline);
		j := j + 1;
	end if;

	tb_intr <= '0';

	-- clear event notice
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFFFFFFFFFF";


	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- force intr requests, check CINT_n, should not be asserted

	address_reg <= FcnForceReg_Addr;
	data_reg <= x"0000000000008000";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- present state - intr bit should also be 1
	address_reg <= FcnStateReg_Addr;
	data_reg <= x"0000000000000000";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- check if event function register has been set
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"0000000000008000";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	if (tb_CINT_n = '1') then
		write(outline, string'("CINT_N Test #4 - Passed..."));
		writeline(output, outline);
		j := j + 1;
	end if;

	tb_intr <= '0';

	write(outline, string'("["));
	write(outline, now);
	write(outline, string'("] END OF CINT_N TEST - "));
	write(outline, integer'image(j));
	write(outline, string'(" out of 4 tests passed."));
	writeline(output, outline);

	passed <= j;

end cint_test; 	

procedure caudio_test (
					  signal address_reg : inout std_logic_vector(63 downto 0);
					  signal data_reg : inout std_logic_vector(63 downto 0);
					  signal target_bar : inout std_logic_vector(63 downto 0);
					  signal master_abort : in std_logic;
					  signal set_master_abort : out std_logic;
					  signal serrn_detected : in std_logic;
					  signal perrn_detected : in std_logic;
					  signal clear_serr : out std_logic;
					  signal clear_disconnect : out std_logic;
					  signal disconnect_detected : in std_logic;
					  signal clear_perr : out std_logic;

                      SIGNAL master1_start_bit : OUT std_logic;
                      SIGNAL master1_done_bit : IN std_logic;
                      SIGNAL master1_addr : OUT std_logic_vector(63 downto 0);
                      SIGNAL master1_command : OUT std_logic_vector(3 downto 0);
                      SIGNAL master1_dword_count : OUT integer;
                      SIGNAL master1_initial_data_delay : OUT integer;
                      SIGNAL master1_next_data_delay : OUT integer;
                      SIGNAL master1_bad_parity_phase: OUT integer;
                      SIGNAL master1_m64bit : OUT std_logic;
                      SIGNAL master1_quiet : OUT std_logic;
                      SIGNAL be_array : OUT BYTE_ARRAY_TYPE;
                      SIGNAL data_array : OUT DATA_ARRAY_TYPE;
					  SIGNAL CLK : IN std_logic;
   					  signal tb_CAUDIO: in std_logic;
				      signal tb_BAM   : out std_logic;
				      signal tb_PWM   : out std_logic;
				      signal passed   : out integer
   					  ) is
begin

	j := 0;
	write(outline, string'("["));
	write(outline, now);
	write(outline, string'("] START OF CAUDIO TEST"));
	writeline(output, outline);


	-- clear event notice
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFFFFFFFFFF";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- supply BAM and PWM inputs
	tb_BAM <= '0';
	tb_PWM <= '1';

	-- disable both audio types, check CAUDIO_n, should be inactive
	address_reg <= FcnMaskReg_Addr;
	data_reg <= x"FFFFFFFF00000000";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	for i in 1 to 2 loop
		wait until (CLK'event and CLK='1');
	end loop;

	if (tb_CAUDIO = '0') then
		write(outline, string'("CAUDIO Test #1 - Passed..."));
		writeline(output, outline);
		j := j + 1;
	end if;

	--enable both, check CAUDIO, should be inactive -> low
	-- write to mask offset, enable bit 5 and 6

	data_reg <= x"FFFFFFFF00000060";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	for i in 1 to 2 loop
		wait until (CLK'event and CLK='1');
	end loop;