cardbus_wrapper_test.tb

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

	           master1_quiet,be_array,data_array,CLK);

	-- read event register
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFF00000008";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- read present state register
	address_reg <= FcnStateReg_Addr;
	data_reg <= x"FFFFFFFF0000000B";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- check if CSTSCHG signal is deasserted
	if tb_CSTSCHG = '0' then	
		write(outline, string'("CSTSCHG Test #3e - Event #5 detected, CSTSCHG not asserted. Passed..."));
		writeline(output, outline);
		j := j + 1;
		i := i + 1;
	end if;	

 	-- EVENT #6 of Test #3
	--clear event notice
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFFFFFFFFFF";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	tb_gwake <= '1'; -- bit 4 event

	wait until (CLK'event and CLK='1');

	-- enable WKUP and enable all but READY
	address_reg <= FcnMaskReg_Addr;
	data_reg <= x"FFFFFFFFFFFFC00F";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- read event register
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFF00000010";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- read present state register
	address_reg <= FcnStateReg_Addr;
	data_reg <= x"FFFFFFFF0000001B";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- check if CSTSCHG signal is deasserted
	if tb_CSTSCHG = '0' then	
		write(outline, string'("CSTSCHG Test #3f - Event #6 detected, CSTSCHG not asserted. Passed..."));
		writeline(output, outline);
		j := j + 1;
		i := i + 1;
	end if;	

	if i = 6 then
		k := k + 1;
	end if;

	i := 0; -- reset # of tests passed in this major test 

	-- 	ctu
	-- Test Force Function Events (3 events in total)
	-- Event #1 of Test #4
	write(outline, string'("["));
	write(outline, now);
	write(outline, string'("] Force Function Events Test"));
	writeline(output, outline);

	-- clear event notice
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFFFFFFFFFF";
	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- enable WKUP and all sources
	address_reg <= FcnMaskReg_Addr;
	data_reg <= x"FFFFFFFF0000C01F";
	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- force events
	address_reg <= FcnForceReg_Addr;
	data_reg <= x"FFFFFFFF00000011";
	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- read event register
	address_reg <= FcnEventReg_Addr;
	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- check if CSTSCHG signal is asserted
	if tb_CSTSCHG = '1' then	
		write(outline, string'("CSTSCHG Test #4a - Event #1 detected, CSTSCHG asserted. Passed..."));
		writeline(output, outline);
		j := j + 1;
		i := i + 1;
	end if;	

	-- Event #2 of Test #4				 
	-- force events
	address_reg <= FcnForceReg_Addr;
	data_reg <= x"FFFFFFFF00008007";
	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- read event register
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFF00008017";
	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- check if CSTSCHG signal is asserted
	if tb_CSTSCHG = '1' then	
		write(outline, string'("CSTSCHG Test #4b - Event #2 detected, CSTSCHG asserted. Passed..."));
		writeline(output, outline);
		j := j + 1;
		i := i + 1;
	end if;	

	-- Event #3 of Test #4
	-- disable WKUP and enable all sources
	address_reg <= FcnMaskReg_Addr;
	data_reg <= x"FFFFFFFF0000801F";
	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- force events
	address_reg <= FcnForceReg_Addr;
	data_reg <= x"FFFFFFFF00000008";
	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- read event register
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFF0000801F";
	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- check if CSTSCHG signal is deasserted
	if tb_CSTSCHG = '0' then	
		write(outline, string'("CSTSCHG Test #4c - Event #3 detected, CSTSCHG not asserted. Passed..."));
		writeline(output, outline);
		j := j + 1;
		i := i + 1;
	end if;

	if i = 3 then
		k := k + 1;
	end if;

	i := 0; -- reset # of tests passed in this major test 
	write(outline, string'("["));
	write(outline, now);
	write(outline, string'("] Test Invalid Writes to Function Event and State Registers."));
	writeline(output, outline);

	tb_wp <= '0';  		-- bit 0
	tb_ready <= '0';	-- bit 1
	tb_bvd(2) <= '0';	-- bit 2
	tb_bvd(1) <= '0';	-- bit 3
	tb_gwake <= '0';	-- bit 4
	tb_intr <= '0';		-- bit 15

	-- clear event notice
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFFFFFFFFFF";
	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	tb_wp <= '0';  		-- bit 0
	tb_ready <= '1';	-- bit 1
	tb_bvd(2) <= '0';	-- bit 2
	tb_bvd(1) <= '1';	-- bit 3
	tb_gwake <= '0';	-- bit 4
	tb_intr <= '1';		-- bit 15

	--	read event register
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFF0000000A";
	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);
	-- read present state register
	address_reg <= FcnStateReg_Addr;
	data_reg <= x"FFFFFFFF0000800A";
	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);
	-- write 0 to event register (should have no effect)
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFF00000000";
	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- write to present state register (should have no effect)
	address_reg <= FcnStateReg_Addr;
	data_reg <= x"FFFFFFFF12345678";
	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	--	read event register
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFF0000000A";
	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);
	-- read present state register
	address_reg <= FcnStateReg_Addr;
	data_reg <= x"FFFFFFFF0000800A";
	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	write(outline, string'("CSTSCHG Test #5 - Passed..."));
	writeline(output, outline);
	
	k := K + 1;
	j := j + 1;

	tb_wp <= '0';  		-- bit 0
	tb_ready <= '0';	-- bit 1
	tb_bvd(2) <= '0';	-- bit 2
	tb_bvd(1) <= '0';	-- bit 3
	tb_gwake <= '0';	-- bit 4
	tb_intr <= '0';		-- bit 15

	-- clear event notice
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFFFFFFFFFF";
	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	write(outline, string'("["));
	write(outline, now);
	write(outline, string'("] END OF CSTSCHG TEST - "));
	write(outline, integer'image(k));
	write(outline, string'(" out of 5 major CSTSCHG tests category passed."));
	write(outline, integer'image(j));
	write(outline, string'(" out of 14 total CSTSCHG tests passed."));
	writeline(output, outline);

	passed <= j;
	K := 0;
	i := 0;
end cstschg_test; 	

procedure cint_test (
					  signal address_reg : inout std_logic_vector(63 downto 0);
					  signal data_reg : inout std_logic_vector(63 downto 0);
					  signal target_bar : inout std_logic_vector(63 downto 0);
					  signal master_abort : in std_logic;
					  signal set_master_abort : out std_logic;
					  signal serrn_detected : in std_logic;
					  signal perrn_detected : in std_logic;
					  signal clear_serr : out std_logic;
					  signal clear_disconnect : out std_logic;
					  signal disconnect_detected : in std_logic;
					  signal clear_perr : out std_logic;

                      SIGNAL master1_start_bit : OUT std_logic;