cardbus_wrapper_test.tb

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

	-- read event register
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFF00000007";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- read present state register
	address_reg <= FcnStateReg_Addr;
	data_reg <= x"FFFFFFFF00000007";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);


	-- check if CSTSCHG signal is asserted
	if tb_CSTSCHG = '1' then	
		write(outline, string'("CSTSCHG Test #1a - Passed..."));
		writeline(output, outline);
		j := j + 1;
		i := i + 1;
	end if;		

	-- clear status change event and check if CSTSCHG is deasserted
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFFFFFFFFFF";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

--	write(outline, now);
--	writeline(output, outline);
	wait until (CLK'event and CLK='1');
	
	-- check if CSTSCHG signal is deasserted
	if tb_CSTSCHG = '0' then	
		write(outline, string'("CSTSCHG Test #1b - Passed..."));
		writeline(output, outline);
		j := j + 1;
		i := i + 1;
	end if;		

	if i = 2 then
		k := k + 1;
	end if;

	i := 0; -- reset # of tests passed in this major test 

	-- ctu CSTSCHG TEST #2
	-- change first 3 bits to 0, and last 3 bits to 1 
	-- status changed should assert
	-- present state should be updated
	-- function event reg should be updated

	write(outline, string'("Toggling state inputs..."));
	writeline(output, outline);

	tb_wp <= '0';  		-- bit 0
	tb_ready <= '0';	-- bit 1
	tb_bvd(2) <= '0';	-- bit 2
	tb_bvd(1) <= '1';	-- bit 3
	tb_gwake <= '1';	-- bit 4
	tb_intr <= '1';		-- bit 15

	-- read event register
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFF0000001F";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- read present state register
	address_reg <= FcnStateReg_Addr;
	data_reg <= x"FFFFFFFF00008018";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);


	-- check if CSTSCHG signal is asserted
	if tb_CSTSCHG = '1' then	
		write(outline, string'("CSTSCHG Test #2a - Passed..."));
		writeline(output, outline);
		j := j + 1;
		i := i + 1;
	end if;		

	-- clear status change event and check if CSTSCHG is deasserted
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFFFFFFFFFF";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

--	write(outline, now);
--	writeline(output, outline);
	wait until (CLK'event and CLK='1');

	-- check if CSTSCHG signal is deasserted
	if tb_CSTSCHG = '0' then	
		write(outline, string'("CSTSCHG Test #2b - Passed..."));
		writeline(output, outline);
		j := j + 1;
		i := i + 1;
	end if;

	if i = 2 then
		k := k + 1;
	end if;

	i := 0; -- reset # of tests passed in this major test 

	--ctu notes
	-- Test Event Function and Mask Register Events (6 events in total)

	-- enable and disable WKUP, change states, check event and interrupt		
	tb_wp <= '0';  		-- bit 0
	tb_ready <= '0';	-- bit 1
	tb_bvd(2) <= '0';	-- bit 2
	tb_bvd(1) <= '0';	-- bit 3
	tb_gwake <= '0';	-- bit 4
	tb_intr <= '0';		-- bit 15

	write(outline, string'("Masking event sources for SCTSCHG generation."));
	writeline(output, outline);

 	-- EVENT #1 of Test #3
	-- enable WKUP and all sources
	address_reg <= FcnMaskReg_Addr;
	data_reg <= x"FFFFFFFFFFFFCFFF";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- read event register
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFF00000018";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- read present state register
	address_reg <= FcnStateReg_Addr;
	data_reg <= x"FFFFFFFF00000000";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- check if CSTSCHG signal is asserted
	if tb_CSTSCHG = '1' then	
		write(outline, string'("CSTSCHG Test #3a - Event #1 detected, CSTSCHG asserted. Passed..."));
		writeline(output, outline);
		j := j + 1;
		i := i + 1;
	end if;		

 	-- EVENT #2 of Test #3
	-- disable WKUP -CSTSCHG will not be flagged
	address_reg <= FcnMaskReg_Addr;
	data_reg <= x"FFFFFFFFFFFF8FFF";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- check if CSTSCHG signal is deasserted
	if tb_CSTSCHG = '0' then	
		write(outline, string'("CSTSCHG Test #3b - Event #2 detected, CSTSCHG not asserted. Passed..."));
		writeline(output, outline);
		j := j + 1;
		i := i + 1;
	end if;		

	--write to mask, change present states, read to make sure updated but no interrupt
 	-- EVENT #3 of Test #3
	--clear event notice
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFFFFFFFFFF";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	tb_wp <= '1'; -- bit 0 event

	wait until (CLK'event and CLK='1');

	-- enable WKUP and enable all but WP
	address_reg <= FcnMaskReg_Addr;
	data_reg <= x"FFFFFFFFFFFFC01E";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- read event register
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFF00000001";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- read present state register
	address_reg <= FcnStateReg_Addr;
	data_reg <= x"FFFFFFFF00000001";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- check if CSTSCHG signal is deasserted
	if tb_CSTSCHG = '0' then	
		write(outline, string'("CSTSCHG Test #3c - Event #3 detected, CSTSCHG not asserted. Passed..."));
		writeline(output, outline);
		j := j + 1;
		i := i + 1;
	end if;		

	--write to mask, change present states, read to make sure updated but no interrupt
 	-- EVENT #4 of Test #3
	--clear event notice
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFFFFFFFFFF";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	tb_ready <= '1'; -- bit 1 event

	wait until (CLK'event and CLK='1');

	-- enable WKUP and enable all but READY
	address_reg <= FcnMaskReg_Addr;
	data_reg <= x"FFFFFFFFFFFFC01D";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- read event register
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFF00000002";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- read present state register
	address_reg <= FcnStateReg_Addr;
	data_reg <= x"FFFFFFFF00000003";

	pci_access(address_reg,data_reg,MEM_READ,x"FF",1,1,1,0,'0','0',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	-- check if CSTSCHG signal is deasserted
	if tb_CSTSCHG = '0' then	
		write(outline, string'("CSTSCHG Test #3d - Event #4 detected, CSTSCHG not asserted. Passed..."));
		writeline(output, outline);
		j := j + 1;
		i := i + 1;
	end if;		

 	-- EVENT #5 of Test #3
	--clear event notice
	address_reg <= FcnEventReg_Addr;
	data_reg <= x"FFFFFFFFFFFFFFFF";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,
	           master1_quiet,be_array,data_array,CLK);

	tb_bvd <= "01"; -- bit 2/3 event

	wait until (CLK'event and CLK='1');

	-- enable WKUP and enable all but BVD
	address_reg <= FcnMaskReg_Addr;
	data_reg <= x"FFFFFFFFFFFFC013";

	pci_access(address_reg,data_reg,MEM_WRITE,x"FF",1,1,1,0,'0','1',
	           master1_start_bit,master1_done_bit,master1_addr,master1_command,master1_dword_count,
	           master1_initial_data_delay,master1_next_data_delay,master1_bad_parity_phase,master1_m64bit,