dmaregrd.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

--------------------------------------------------------------------------------
--
-- File : dmaregrd.vhd
-- Last Modification: 06/26/2001
--
-- Created In SpDE Version: SpDE 8.22
-- Author :	Richard Yuan, QuickLogic Corporation
-- Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--	
-- Description : This is a block in the QL5(3/4)32-33 programmable logic region.
--	It contains the following sections:
--		clock frequency control registers
--		DMA performance measurement registers
--		programmable retry/wait-state control registers
--		some target memory
--
-- Hierarchy:
--	This file represents the dmaregrd block in pci5432_208.sch.
--
-- History:	
--	Date	        Author					Version
--  06/26/01		Richard Yuan			1.0
--		- Header reorganized to conform to coding standard.
--
--------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity dmaregrd is 

port (
    clk, clr, DMAWrEn: in std_logic;
    PCI_data: in std_logic_vector(31 downto 0);
    CBE: in std_logic_vector(3 downto 0);
    DMARdEn: in std_logic;
    adr: in std_logic_vector(9 downto 2);
    dataout: out std_logic_vector(31 downto 0);
    PCI_Wr: in std_logic;
    clkspd: out std_logic_vector(2 downto 0);
    IncrAddr, LoadAddr: in std_logic;
    ledcntrl: out std_logic;
    led: out std_logic_vector(7 downto 0);
    Usr_Rdy, Usr_Stop: out std_logic
    );
end dmaregrd;

architecture behavioral of dmaregrd is

signal perfcount: unsigned(19 downto 0);
signal DMARdWr, ClkSpdHit, TControlHit: std_logic;
signal StopReg, WaitReg: std_logic_vector(2 downto 0);
signal WaitCount, RetryCount, StopCount: unsigned(2 downto 0);
signal PerfCntLd: std_logic;
signal ram_read_data: std_logic_vector(31 downto 0);
signal ram0_we, ram1_we, ram2_we, ram3_we: std_logic;

signal clkspd_local: std_logic_vector(2 downto 0);
signal led_local: std_logic_vector(7 downto 0);
signal Usr_Stop_local: std_logic;
signal ledcntrl_local: std_logic;
-- signal to remember if Usr_Rdy has been asserted
signal Usr_Rdy_asserted: std_logic;
signal Usr_Rdy_local: std_logic;

component r128a8
port (wa, ra: in std_logic_vector (6 downto 0);
		wd : in std_logic_vector (7 downto 0);
        rd : out std_logic_vector (7 downto 0);
        we, wclk: in std_logic );
end component;

begin
    clkspd   <= clkspd_local;
    led      <= led_local;
    Usr_Stop <= Usr_Stop_local;
    ledcntrl <= ledcntrl_local;
	Usr_Rdy  <= Usr_Rdy_local;

    -- Keep last state of DMARxEn and DMATxEn
    process (clk)
    begin
        if clk'event and clk = '1' then
            DMARdWr <= DMAWrEn or DMARdEn;
        end if;
    end process;  

    -- Initialize Counter as soon as DMARxEn or DMATxEn is set to 1
    PerfCntLd <= not (DMARdWr) and (DMAWrEn or DMARdEn);
    
    process (clk, clr)
    begin
        if clr = '1' then perfcount <= (others => '0');
        elsif clk'event and clk = '1' then
            if PerfCntLd  = '1' then perfcount <= (others => '0');
            elsif DMARdWr = '1' then perfcount <= perfcount + 1;
            end if;
        end if;
    end process;
        
    process (adr, perfcount, clkspd_local, ram_read_data, led_local, ledcntrl_local, RetryCount,
                                                                StopReg, WaitReg)
    begin
        ClkSpdHit   <= '0';
        TControlHit <= '0';
        dataout     <= ram_read_data;

        case adr is
            when "01000100" => dataout(19 downto  0) <= std_logic_vector(perfcount); -- address 0x110
                               dataout(31 downto 20) <= (others => '0'); 
            when "01000101" => ClkSpdHit   <= '1';       -- address 0x114
                               dataout( 2 downto  0) <= clkspd_local;
                               dataout(31 downto  3) <= (others => '0');
            when "01000110" => TControlHit <= '1';       -- address 0x118
                               dataout     <= "00000" & std_logic_vector(RetryCount) &
                                              "0" & StopReg & "0" & WaitReg &
                                              "0000000" & ledcntrl_local & led_local;
            when  others    => null;
        end case;

    end process;

    process (clk, clr)
    begin
        if clr = '1' then  clkspd_local <= "110"; -- defaults to 42 MHz (3X clock)
        elsif clk'event and clk = '1' then
            if IncrAddr = '1' and PCI_Wr = '1' and ClkSpdHit = '1' and CBE(0) = '0' then
                clkspd_local <= PCI_data(2 downto 0);
            end if;
        end if;
    end process;

    process (clk, clr)
    begin
        if clr = '1' then
            ledcntrl_local  <= '0'; -- defaults to FIFO/buffer status
            led_local <= (others => '0');
        else
            if clk'event and clk = '1' then
                if IncrAddr = '1' and PCI_Wr = '1' and TControlHit = '1' then
                    if CBE(0) = '0' then led_local <= PCI_data(7 downto 0); end if;
                    if CBE(1) = '0' then ledcntrl_local  <= PCI_data(8); end if;
                end if;
            end if;
        end if;
    end process;

    -- Programmable Wait State Control
    process (clk, clr)
    begin
        if clr = '1' then
            WaitCount <= "000";
            WaitReg   <= "000";
			Usr_Rdy_Asserted <= '0';
        elsif clk'event and clk = '1' then
            if LoadAddr = '1' or IncrAddr = '1' or (PCI_Wr = '1' and Usr_Rdy_local = '1') then
            	WaitCount <= "000";
            elsif not (std_logic_vector(WaitCount) = WaitReg) then
                WaitCount <= WaitCount + 1;
            end if;
            if IncrAddr = '1' and PCI_Wr = '1' and TControlHit = '1' and CBE(2) = '0' then 
                WaitReg <= PCI_data(18 downto 16);
            end if;
			if LoadAddr = '1' or IncrAddr = '1' then
				Usr_Rdy_Asserted <= '0';
			elsif Usr_Rdy_local = '1' then
				Usr_Rdy_Asserted <= '1';
			end if;
        end if;
    end process;
    
	process (PCI_Wr, WaitCount, WaitReg, Usr_Rdy_Asserted)
	begin
		if PCI_Wr = '1' then
    		if (std_logic_vector(WaitCount) = WaitReg and Usr_Rdy_Asserted = '0') or WaitReg = "000" then
				Usr_Rdy_local <= '1';
			else
				Usr_Rdy_local <= '0';
			end if;
		else
    		if std_logic_vector(WaitCount) = WaitReg then
				Usr_Rdy_local <= '1';
			else
				Usr_Rdy_local <= '0';
			end if;
		end if;
	end process;

    -- Programmable Stop Cycle Control
    process (clk, clr)
    begin
        if clr = '1' then 
            StopCount <= "000";
            StopReg   <= "000";
        elsif clk'event and clk = '1' then
            if LoadAddr = '1' or Usr_Stop_local = '1' then StopCount <= "000";
            elsif not (std_logic_vector(StopCount) = StopReg) and IncrAddr = '1' then
                StopCount <= StopCount + 1;
            end if;
            if IncrAddr = '1' and PCI_Wr = '1' and 
               TControlHit = '1' and not (CBE(2) = '1') then
                StopReg <= PCI_data(22 downto 20);
            end if;
        end if;
    end process;
        
    -- Programmable Retry Control
    process (clk, clr)
    begin
        if clr = '1' then  RetryCount <= "000";
        elsif clk'event and clk = '1' then
            if IncrAddr = '1' and PCI_Wr = '1' and 
               TControlHit = '1' and not (CBE(3) = '1') then
                RetryCount <= unsigned(PCI_data(26 downto 24));
            elsif not (std_logic_vector(RetryCount) = "000") and LoadAddr = '1' then
                RetryCount <= RetryCount - 1;
            end if;
        end if;
    end process;

    process (StopReg, RetryCount, StopCount)
    begin
        if StopReg = "000" then
            if not (std_logic_vector(RetryCount) = "000") then Usr_Stop_local <= '1';
            else Usr_Stop_local <= '0';
            end if;
        elsif std_logic_vector(StopCount) = StopReg then Usr_Stop_local <= '1';
        else Usr_Stop_local <= '0';
		end if;

    end process;

    ram0_we <= '1' when not (CBE(0) = '1') and IncrAddr = '1' and PCI_Wr = '1' else '0';
    ram1_we <= '1' when not (CBE(1) = '1') and IncrAddr = '1' and PCI_Wr = '1' else '0';
    ram2_we <= '1' when not (CBE(2) = '1') and IncrAddr = '1' and PCI_Wr = '1' else '0';
    ram3_we <= '1' when not (CBE(3) = '1') and IncrAddr = '1' and PCI_Wr = '1' else '0';

    target_ram0: r128a8 Port Map (wa=>adr(8 downto 2), ra=>adr(8 downto 2), wd=>PCI_data( 7 downto  0),
                                  rd=>ram_read_data( 7 downto  0), we=>ram0_we, wclk=>clk);
    target_ram1: r128a8 Port Map (wa=>adr(8 downto 2), ra=>adr(8 downto 2), wd=>PCI_data(15 downto  8),
                                  rd=>ram_read_data(15 downto  8), we=>ram1_we, wclk=>clk); 
    target_ram2: r128a8 Port Map (wa=>adr(8 downto 2), ra=>adr(8 downto 2), wd=>PCI_data(23 downto 16),
                                  rd=>ram_read_data(23 downto 16), we=>ram2_we, wclk=>clk);
    target_ram3: r128a8 Port Map (wa=>adr(8 downto 2), ra=>adr(8 downto 2), wd=>PCI_data(31 downto 24),
                                  rd=>ram_read_data(31 downto 24), we=>ram3_we, wclk=>clk); 

end behavioral;