r128a8.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

------------------------------------------------------------------------
-- File : r128a8.vhd
-- Design Date: June 9, 1998
-- Creation Date: Sat Jan 27 16:44:54 2001

-- Created By SpDE Version: SpDE 9.0 Build8
-- Author: Ed Bezeg, Robert Maul, QuickLogic Corporation,
-- Copyright (C) 1998, Customers of QuickLogic may copy and modify this
-- file for use in designing QuickLogic devices only.
-- Description : This file is autogenerated structural code that describes
-- the connectivity of cascaded RAM blocks (called RAM banks) using
-- QuickLogic's RAM block resources.
------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

   -- inputs: =wa[6:0]=,=ra[6:0]=,=wd[7:0]=,we,wclk
   -- outputs: =rd[7:0]=
entity r128a8 is port (
   we,wclk : in std_logic;
   wa, ra : in std_logic_vector (6 downto 0);
   wd : in std_logic_vector (7 downto 0);
   rd : out std_logic_vector (7 downto 0));
end r128a8;

architecture arch of r128a8 is
signal GND : std_logic;
signal VCC : std_logic;
signal WD_reg : std_logic_vector (8 downto 0);
signal RD_reg1 : std_logic_vector (8 downto 0);
attribute syn_black_box : boolean;
attribute syn_macro : integer;
component RAM128X9
   port (WA, RA : in std_logic_vector (6 downto 0);
         WD : in std_logic_vector (8 downto 0);
         RD : out std_logic_vector (8 downto 0);
         WE, RE, WCLK, RCLK, ASYNCRD : in std_logic);
end component ;
attribute syn_black_box of RAM128X9 : component is true;
attribute syn_macro of RAM128X9 : component is 1;
begin
GND <= '0';
VCC <= '1';
rd <= RD_reg1(8 downto 1) after 1 ns;
WD_reg <= ( wd & GND ) after 1 ns;
r128a8I1 : RAM128X9
   port map(WA => wa, RA => ra, WD => WD_reg(8 downto 0), RD => RD_reg1, 
            WE => we, RE => GND, WCLK => wclk, RCLK => GND, ASYNCRD => VCC);
end arch;