f128x4_25um.tb

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

------------------------------------------------------------------------
-- File : f128x4_25um.tb
-- Design Date: June 9, 1998
-- Creation Date : Mon May 06 13:42:48 2002

-- Created By SpDE Version : SpDE 9.3 Alpha Build3
-- Author: Robert Maul, QuickLogic Corporation,
-- Copyright (C) 1998, Customers of QuickLogic may copy and modify this
-- file for use in designing QuickLogic devices only.
-- Description: This is a sample test bench for your FIFO.
-- data is loaded in then read back
-- The intended use of this file is to help users verify that the
-- FIFO that is generated by SpDE is functionally correct.
------------------------------------------------------------------------

entity test_f128x4_25um is
end test_f128x4_25um;

architecture behave of test_f128x4_25um is

component f128x4_25um
   port (pop : in std_logic;
         push : in std_logic;
         clk : in std_logic;
         rst : in std_logic;
         din : in std_logic_vector (3 downto 0);
         dout  : out std_logic_vector (3 downto 0);
         emptyn : out std_logic;
         fulln  : out std_logic);
end component;

signal emptyn: std_logic;
signal fulln : std_logic;
signal pop  : std_logic;
signal push : std_logic;
signal clk  : std_logic;
signal rst  : std_logic;
signal din  : std_logic_vector (3 downto 0);
signal dout : std_logic_vector (3 downto 0);
signal stopClock : boolean;

signal i    : std_logic_vector (3 downto 0);
constant period: time := 100 ns;

begin -- fifo is loaded with data and then, as it is unloaded, a
      -- check is performed to see if the same data is read back.

   m : f128x4_25um
      port map (clk  => clk,
                rst  => rst,
                pop  => pop,
                push => push,
                din  => din,
                emptyn => emptyn,
                fulln  => fulln,
                dout  => dout);
   Reset: process
   begin
      rst <= '1';
      wait for period/4;
      rst <= '0';
      wait;
   end process Reset;

   ClockGenerator: process
   begin
      while TRUE loop
         clk <= '0';
         wait for period/2;
         clk <= '1';
         wait for period/2;
      end loop;
   end process ClockGenerator;

   Stimulus: process
   begin
      i <= "0000";
      while TRUE loop
         wait for period;
         din <= i;
         i <= i + 1;
      end loop;
   end process Stimulus;

   loadAndUnLoad : process
   begin
      stopClock <= FALSE;
      push <= '1';
      pop <= '0';

      wait for period * 130;  -- fill up fifo

      push <= '0';
      pop <= '1';

      wait for period * 130;  -- unload up fifo
      stopClock <= TRUE;
   end process loadAndUnLoad;
end behave;

configuration behave_test_f128x4_25um of test_f128x4_25um is
for behave
end for;
end behave_test_f128x4_25um;