dcount8.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

--------------------------------------------------------------------------------
--
-- File : dcount8.vhd
-- Last Modification: 06/26/2001
--
-- Created In SpDE Version: SpDE 8.22
-- Author :	Richard Yuan, QuickLogic Corporation
-- Copyright (C) 2001, Licensed Customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--	
-- Description :
--	This file implements an 8-bit down counter converted from schematic.
--	 
-- Hierarchy:
--	The dcount8 entity is to be used in dmacntrl.vhd.
--
-- History:	
--	Date	        Author					Version
--	06/26/01		Richard Yuan			1.0
--		- Header added to conform to coding standard.
--
--------------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;

entity dcount8 is
      Port (     CLR : In    STD_LOGIC;
                  EN : In    STD_LOGIC;
                 CLK : In    STD_LOGIC;
                LOAD : In    STD_LOGIC;
                   D : In    STD_LOGIC_VECTOR (7 downto 0);
                   Q : Out   STD_LOGIC_VECTOR (7 downto 0) );
end dcount8;


architecture SCHEMATIC of dcount8 is

	constant VCC : STD_LOGIC := '1';
   signal      N_3 : STD_LOGIC;
   signal Q_DUMMY : STD_LOGIC_VECTOR  (7 downto 0);

   component DCNTX4B
      Port (     CLK : In    STD_LOGIC;
                 CLR : In    STD_LOGIC;
                   D : In    STD_LOGIC_VECTOR  (3 downto 0);
                 ENG : In    STD_LOGIC;
                 ENP : In    STD_LOGIC;
                 ENT : In    STD_LOGIC;
                LOAD : In    STD_LOGIC;
                   Q : Out   STD_LOGIC_VECTOR  (3 downto 0);
                 RCO : Out   STD_LOGIC );
   end component;

   component DCNTX4C
      Port (     CLK : In    STD_LOGIC;
                 CLR : In    STD_LOGIC;
                   D : In    STD_LOGIC_VECTOR  (3 downto 0);
                 ENG : In    STD_LOGIC;
                 ENP : In    STD_LOGIC;
                 ENT : In    STD_LOGIC;
                LOAD : In    STD_LOGIC;
                   Q : Out   STD_LOGIC_VECTOR  (3 downto 0) );
   end component;

begin


   Q(7 downto 0) <= Q_DUMMY(7 downto 0);
   I3 : DCNTX4B
      Port Map ( CLK=>CLK, CLR=>CLR, D(3 downto 0)=>D(3 downto 0),
                 ENG=>EN, ENP=>VCC, ENT=>VCC, LOAD=>LOAD,
                 Q(3 downto 0)=>Q_DUMMY(3 downto 0), RCO=>N_3 );
   I6 : DCNTX4C
      Port Map ( CLK=>CLK, CLR=>CLR, D(3 downto 0)=>D(7 downto 4),
                 ENG=>EN, ENP=>N_3, ENT=>N_3, LOAD=>LOAD,
                 Q(3 downto 0)=>Q_DUMMY(7 downto 4) );

end SCHEMATIC;