📄 cmd_monitor.tb
字号:
----------------------------------------------------------------------------
--
-- File: cmd_monitor.tb
-- Last Modification: November 12, 2002
--
-- Author: Claire Pian Tu, QuickLogic Corporation
-- Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--
-- Description:
-- This is a test bench file that allows users to monitor PCI commands,
-- configuration space and memory address being accessed.
--
-- Hierarchy:
-- This file is a part of the top level test bench file
--
-- History:
-- Date Author Version
-- 10/07/02 Claire Pian Tu 1.0
-- -- Initial release.
-- 10/17/02 Claire Pian Tu 1.1
-- --Added code to monitor configuration space
-- 10/19/02 Claire Pian Tu 1.2
-- --Added code to differientiate consecutive PCI commands
-- 10/29/02 Claire Pian Tu 1.3
-- --Added memory address signal for probing
-- 11/07/02 Claire Pian Tu 1.4
-- --Added comments,updated readme, changed file
-- extension to .tb
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity cmd_monitor is
port (
ad : in std_logic_vector(63 downto 0);
cben : in std_logic_vector(7 downto 0);
clk : in std_logic;
devseln : in std_logic;
framen : in std_logic;
idsel : in std_logic;
irdyn : in std_logic;
par : in std_logic;
perrn : in std_logic;
rstn : in std_logic;
serrn : in std_logic;
stopn : in std_logic;
trdyn : in std_logic;
test_type : in std_logic_vector(7 downto 0);
cmd_mon : out std_logic_vector(7 downto 0)
);
end cmd_monitor;
architecture cmd_monitor_arch1 of cmd_monitor is
-- declare PCI_CMD type
type state_type is (
Idle, -- Idle (default)
IA, --0 Interrupt_Ack
I_A,
SC, --1 Special_Cycle
S_C,
IO_R, --2 IO Read
I_O_R,
IO_W, --3 IO Write
I_O_W,
Res4, --4 Reserved
Res_4,
Res5, --5 Reserved
Res_5,
MR, --6 Mem Read
M_R,
MW, --7 Mem Write
M_W,
Res8, --8 Reserved
Res_8,
Res9, --9 Reserved
Res_9,
CR, --A Config Read
C_R,
CW, --B Config Write
C_W,
Mem_R_M, --C Mem Read Multiple
MRM,
D_A_C, --D Dual Address cycle
DAC,
M_R_L, --E Mem Read Line
MRL,
M_W_I, --F Mem Write & Invalidate
MWI
);
type config_space is (
None,
Dev_Vend,
Stat_Cmd,
Clas_Rev,
BHLC,
BAR0,
BAR1,
BAR2,
BAR3,
BAR4,
BAR5,
Card_CIS,
Sub_ID,
Expan_ROM,
Res34h,
Res38h,
Max_Min_IR
);
-- this test_suite state type can be configured to suit your own series of tests
-- just add and remove these values as necessary.
-- but remember to update the change_tests process as well as values assigned in your
-- test bench.
type test_suite is (
no_tests,
initialization,
config,
dma_transfers,
byte_enable_test,
pci_cmd_test,
pci_compliance_test,
customer_specific_test
);
signal PCI_CMD: state_type;
signal PCI_CMD_l: state_type;
signal config_add: config_space;
signal test_state: test_suite;
signal framen_l : std_logic;
signal mem_address : std_logic_vector(31 downto 0);
begin
framen_l <= 'H';
cmd_mon(7 downto 0) <= (others=> 'H');
--config_add <= None;
--PCI_CMD <= Idle;
latch_framen: process (clk)
begin
framen_l <= not framen;
end process latch_framen;
change_state: process (framen_l)
begin
-- wait until FALLING_EDGE(framen);
if (rstn = '0') then
PCI_CMD <= Idle;
PCI_CMD_l <= Idle;
elsif (framen_l = '1') then
case cben(3 downto 0) is
when x"0" =>
if (PCI_CMD_l = IA) then
-- PCI_CMD <= I_A;
PCI_CMD_l <= I_A;
else
PCI_CMD <= IA;
PCI_CMD_l <= IA;
end if;
config_add <= None;
when x"1" =>
if (PCI_CMD_l = SC) then
--PCI_CMD <= S_C;
PCI_CMD_l <= S_C;
else
PCI_CMD <= SC;
PCI_CMD_l <= SC;
end if;
config_add <= None;
when x"2" =>
if (PCI_CMD_l = IO_R) then
-- PCI_CMD <= I_O_R;
PCI_CMD_l <= I_O_R;
else
PCI_CMD <= IO_R;
PCI_CMD_l <= IO_R;
end if;
config_add <= None;
when x"3" =>
if (PCI_CMD_l = IO_W) then
-- PCI_CMD <= I_O_W;
PCI_CMD_l <= I_O_W;
else
PCI_CMD <= IO_W;
PCI_CMD_l <= IO_W;
end if;
config_add <= None;
when x"4" =>
if (PCI_CMD_l = Res4) then
-- PCI_CMD <= Res_4;
PCI_CMD_l <= Res_4;
else
PCI_CMD <= Res4;
PCI_CMD_l <= Res4;
end if;
config_add <= None;
when x"5" =>
if (PCI_CMD_l = Res5) then
-- PCI_CMD <= Res_5;
PCI_CMD_l <= Res_5;
else
PCI_CMD <= Res5;
PCI_CMD_l <= Res5;
end if;
config_add <= None;
when x"6" =>
if (PCI_CMD_l = MR) then
-- PCI_CMD <= M_R;
PCI_CMD_l <= M_R;
else
PCI_CMD <= MR;
PCI_CMD_l <= MR;
end if;
mem_address <= ad(31 downto 0);
config_add <= None;
when x"7" =>
if (PCI_CMD_l = MW) then
-- PCI_CMD <= M_W;
PCI_CMD_l <= M_W;
else
PCI_CMD <= MW;
PCI_CMD_l <= MW;
end if;
mem_address <= ad(31 downto 0);
config_add <= None;
when x"8" =>
if (PCI_CMD_l = Res8) then
-- PCI_CMD <= Res_8;
PCI_CMD_l <= Res_8;
else
PCI_CMD <= Res8;
PCI_CMD_l <= Res8;
end if;
config_add <= None;
when x"9" =>
if (PCI_CMD_l = Res9) then
-- PCI_CMD <= Res_9;
PCI_CMD_l <= Res_9;
else
PCI_CMD <= Res9;
PCI_CMD_l <= Res9;
end if;
config_add <= None;
when x"A" =>
if (PCI_CMD_l = CR) then
-- PCI_CMD <= C_R;
PCI_CMD_l <= C_R;
else
PCI_CMD <= CR;
PCI_CMD_l <= CR;
end if;
case ad(7 downto 0) is
when x"00" => config_add <= Dev_Vend;
when x"04" => config_add <= Stat_Cmd;
when x"08" => config_add <= Clas_Rev;
when x"0C" => config_add <= BHLC;
when x"10" => config_add <= BAR0;
when x"14" => config_add <= BAR1;
when x"18" => config_add <= BAR2;
when x"1C" => config_add <= BAR3;
when x"20" => config_add <= BAR4;
when x"24" => config_add <= BAR5;
when x"28" => config_add <= Card_CIS;
when x"2C" => config_add <= Sub_ID;
when x"30" => config_add <= Expan_ROM;
when x"34" => config_add <= Res34h;
when x"38" => config_add <= Res38h;
when x"3C" => config_add <= Max_Min_IR;
when others => config_add <= None;
end case;
when x"B" =>
if (PCI_CMD_l = CW) then
-- PCI_CMD <= C_W;
PCI_CMD_l <= C_W;
else
PCI_CMD <= CW;
PCI_CMD_l <= CW;
end if;
case ad(7 downto 0) is
when x"00" => config_add <= Dev_Vend;
when x"04" => config_add <= Stat_Cmd;
when x"08" => config_add <= Clas_Rev;
when x"0C" => config_add <= BHLC;
when x"10" => config_add <= BAR0;
when x"14" => config_add <= BAR1;
when x"18" => config_add <= BAR2;
when x"1C" => config_add <= BAR3;
when x"20" => config_add <= BAR4;
when x"24" => config_add <= BAR5;
when x"28" => config_add <= Card_CIS;
when x"2C" => config_add <= Sub_ID;
when x"30" => config_add <= Expan_ROM;
when x"34" => config_add <= Res34h;
when x"38" => config_add <= Res38h;
when x"3C" => config_add <= Max_Min_IR;
when others => config_add <= None;
end case;
when x"C" =>
if (PCI_CMD_l = Mem_R_M) then
-- PCI_CMD <=MRM;
PCI_CMD_l <= MRM;
else
PCI_CMD <= Mem_R_M;
PCI_CMD_l <= Mem_R_M;
end if;
config_add <= None;
when x"D" =>
if (PCI_CMD_l = D_A_C) then
-- PCI_CMD <= DAC;
PCI_CMD_l <= DAC;
else
PCI_CMD <= D_A_C;
PCI_CMD_l <= D_A_C;
end if;
config_add <= None;
when x"E" =>
if (PCI_CMD_l = M_R_L) then
-- PCI_CMD <= MRL;
PCI_CMD_l <= MRL;
else
PCI_CMD <= M_R_L;
PCI_CMD_l <= M_R_L;
end if;
config_add <= None;
when x"F" =>
if (PCI_CMD_l = M_W_I) then
-- PCI_CMD <= MWI;
PCI_CMD_l <= MWI;
else
PCI_CMD <= M_W_I;
PCI_CMD_l <= M_W_I;
end if;
config_add <= None;
when others =>
PCI_CMD <= Idle;
PCI_CMD_l <= Idle;
config_add <= None;
end case;
end if;
end process change_state;
change_tests: PROCESS (test_type)
-- variable test_started : boolean;
begin
case test_type is
when x"00" => test_state <= no_tests;
when x"01" => test_state <= initialization;
when x"02" => test_state <= config;
when x"03" => test_state <= dma_transfers;
when x"04" => test_state <= byte_enable_test;
when x"05" => test_state <= pci_cmd_test;
when x"06" => test_state <= customer_specific_test;
when x"07" => test_state <= pci_compliance_test;
when others => test_state <= no_tests;
end case;
END PROCESS change_tests;
cmd_mon <= cben;
end cmd_monitor_arch1;⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -