cardbus_wrapper.v

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

/*-----------------------------------------------------------------------
--	  File : cardbus_wrapper.v
--   
--    DESCRIPTION: 
--			This file provides all CardBus signals (in addition to PCI signals),
--			as well as registers and logic to support those new signals.
--
--    HIERARCHY:  
--			 This file is used in the top-level design, to "wrap-around" the PCI core
--
--    AUTHOR: David Shih
--
--    HISTORY: 
--    Date	        Author					Version
--    10/26/03		David Shih				1.0
--		- Initial release
11/27	first version to export to HDL and run logic optimizer in SpDE
--		
-- Copyright (C) 2003, Licensed Customers of QuickLogic may copy and modify this
-- file for use in designing QuickLogic devices only.
--
-- IMPORTANT NOTICE: DISCLAIMER OF WARRANTY
-- This design is provided without warranty of any kind.
-- QuickLogic Corporation does not warrant, guarantee or make any representations
-- regarding the use, or the results of the use, of this design. QuickLogic
-- disclaims all implied warranties, including but not limited to implied
-- warranties of merchantability and fitness for a particular purpose. In addition
-- and without limiting the generality of the foregoing, QuickLogic does not make
-- any warranty of any kind that any item developed based on this design, or any
-- portion of it, will not infringe any copyright, patent, trade secret or other
-- intellectual property right of any person or entity in any country. It is the
-- responsibility of the user of the design to seek licenses for such intellectual
-- property rights where applicable. QuickLogic shall not be liable for any
-- damages arising out of or in connection with the use of the design including
-- liability for lost profit, business interruption, or any other damages whatsoever.
--
-----------------------------------------------------------------------*/

module cardbus_wrapper
	(	// outputs	
		CINT_n,
		CSTSCHG,
		CAUDIO,
		clk_stopped,
		locked,
		owner_access,
		cstschg_rdy,


		// inouts
		cstschg_regs_in,		
		CCLKRUN_n_in,
		CBLOCK_n,
		cstschg_regs_out,		
		CCLKRUN_n_out,
//		CBLOCK_n_out,
		cstschg_regs_oe,		
		CCLKRUN_n_oe,
//		CBLOCK_n_oe,
		
		// inputs
		BAM_in,
		PWM_in,
		clk,
		reset,
		clk_resume,
		addr_phase,
	//	last_cycle,
		framen_d1,
		usr_read,
		usr_write,
		user_addr,
		intr_ps,		
		gwake_ps,
		bvd_ps,
		ready_ps,
		wp_ps,
		BAR_match
	);

// input output ports
input	clk;			// CardBus clock
input	reset;			// CardBus reset
input	BAM_in;			// Binary Amplitude Modulation input signal
input	PWM_in;			// Pulse Width Modulation input signal
input	clk_resume;		// Request to resume CCLK to its normal frequency
input	addr_phase;		// CardBus address phase; connect to core's Usr_Addr_Valid
//input 	last_cycle;		// CardBus user last cycle flag; connect to core's Usr_Last_Cycle_D1
input	framen_d1;		// CardBus FRAME#; connect to core's PCI_FRAMEN_D1
input	usr_read;		// from core, indicates it's a read access
input	usr_write;		// from core, indicates it's a write access
input	[9:0]	user_addr;	// pci addr, width depends on the user
input			intr_ps;				// interrupt present state
input			gwake_ps;				// general wakeup present state
input	[2:1]	bvd_ps;					// battery voltage detect present state
input			ready_ps;				// ready present state
input			wp_ps;					// write protect present state
input			BAR_match;			// CS for BAR in which FcnEventReg are located

input	[31:0]	cstschg_regs_in;		// CSTSCHG registers datapath
output	[31:0]	cstschg_regs_out;		// CSTSCHG registers datapath
output			cstschg_regs_oe;		// CSTSCHG registers datapath = Usr_Read

input	CBLOCK_n;		// CardBus locked-transfer: connect to pin on CardBus
//output	CBLOCK_n_out;		// CardBus locked-transfer: connect to pin on CardBus
//output	CBLOCK_n_oe;		// CardBus locked-transfer: connect to pin on CardBus

input	CCLKRUN_n_in;		// CardBus clock-run
output	CCLKRUN_n_out;		// CardBus clock-run
output	CCLKRUN_n_oe;		// CardBus clock-run

output	CINT_n;			// CardBus interrupt
output	CSTSCHG;		// CardBus status change
output	CAUDIO;		// CardBus audio
output	clk_stopped;	// Qualified CCLK status
output	locked;			// Flag to indicate we are locked target
output	owner_access;	// Flag to indicate we are accessed by lock owner
						// valid only when locked = 1
output	cstschg_rdy;	// Usr_Rdy for CardBus IP

// CAUDIO internal signals
reg			CAUDIO;	// output register
wire 		BAM_en;		// bit 5 of Function Even Mask Register
wire		PWM_en;		// bit 6 of Function Even Mask Register

// CBLOCK# internal signals
reg			cblockn_d1;	// registered version of CBLOCK#
reg	[1:0]	find_lock;	// CBLOCK# counter fsm

// CCLKRUN# internal signals
reg	[1:0]	clk_cnt /* synthesis syn_preserve = 1 */;	// CCLKRUN# counter fsm
reg			locked;		// output register
reg			owner_access;	// output register
// CSTSCHG internal signals
reg		[15:0]	FcnEventReg;
//reg		[4:0]	FcnEventReg;	DS!!!!!!!!! merged.
reg		[15:0]	FcnMaskReg;	   
//reg		[6:0]	FcnMaskReg;	   // DS was 15:14, 6:0
reg				gwake_ls;				// registered general wakeup state
reg		[2:1]	bvd_ls;					// registered battery voltage detect state
reg				ready_ls;				// registered ready state
reg				wp_ls;					// registered write protect state
reg		[31:0]	cstschg_regs_out;		// function event register data path
reg				xfer_on_going;			// flag to indicate that a transfer is happening
wire			gwake_intr;				   // masked GWAKE
wire			bvd_intr;				   // masked BVD
wire			ready_intr;				   // masked READY
wire			wp_intr;				   // masked WP
wire 			event_reg_cs ;		// address decoding for Function
									// Event related registers, which are
									// located in a memory space location
									// indicated by CISTPL_CONFIG_CB in CIS


/*
// CIS interface , implement externally to this IP
output	CIS_read_en;
output	[31:0]	CIS_data_out;
input	[31:0]	CIS_data_in;
output	[9:0]	CIS_addr;

assign	CIS_data_out = CIS_data_in;	  // connect CIS FLASH data bus to core, via MUX
assign	CIS_read_en = BAR_match;	  // read CIS FLASH when BAR5 matches
assign	CIS_addr = user_addr;		  // config space's usr_addr = addr to CIS
									  // BAR_match is also select for above MUX
*/


// CINT# internal signals
// CTU changed such force interrupt and present state interrupt will both generate CINT_n
assign	CINT_n = !((FcnEventReg[15] || intr_ps) && FcnMaskReg[15]);	// active low interrupt, asynchronous to clock.
								// level-mode interrupt:  remain asserted until serviced.
								// Remember to enable interrupt support in config space!

// PME# is MUXed on CSTSCHG (vol.2, sec 6.7)

//CSTSCHG		5.2.11
// set of 4 registers are located in memory space, indicated by CISTPL_CONFIG_CB. (5.2.11.1)
/*
4.4.13
When the SigChg bit is true (set to 1), the Status
Changed signal is asserted when the Changed bit in the Function Configuration and Status register is
true (set to 1), and the signal is negated when the Changed bit is false (reset to 0). The Changed bit is the
logical OR result of the individual changed bits