📄 pci_cmd_test.tf

📁 VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用
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$display("\tMemory Read, %d",$time);
// Memory Read, transfer 16 doublewords
CurRxSize = 32'h10;
CurTxSize = CurRxSize;
LastDMASize = CurRxSize + CurTxSize;
// master read command 3'b011, all byte lanes on, store data in FIFO
DMACtrlReg = {8'b01_1011_01,24'h0};
DMARxTxCntReg = {CurTxSize, CurRxSize};

// write the DMA setup data to the DMA control registers in the master
master_2.data_array[0] = DMARxTxCntReg;
master_2.data_array[1] = CurRxAddr;
master_2.data_array[2] = 32'h11110000 >> 2;
master_2.data_array[3] = DMACtrlReg;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;
master_2.be_array[3] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,4,1,1,1'b0); 
//Wait for Master DMA to complete
for (i = 0; i < 20; i = i + 1) begin
	repeat (20) @(posedge CLK);
	master_2.target_access(32'h2200010C,64'h0,MEM_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
	if (master_2.data_read[25:24] == 2'b00) begin
		$display("\tMaster DMA Completed Successfully");
		i = 300;
		end
	if (master_2.data_read[25:24] == 2'b10) begin
		$display("\tMaster DMA did not complete");
		i = 300;
		end
	end
if (i < 300) $display("\tMaster DMA did not complete (DMA Timeout)");



$display("\tMemory Read Line, %d",$time);
// Memory Read Line, transfer 16 doublewords
CurRxSize = 32'h10;
CurTxSize = CurRxSize;
LastDMASize = CurRxSize + CurTxSize;
// memory read command 3'b111, all byte lanes on, store data in FIFO
DMACtrlReg = {8'b01_1111_01,24'h0};
DMARxTxCntReg = {CurTxSize, CurRxSize};

// write the DMA setup data to the DMA control registers in the master
master_2.data_array[0] = DMARxTxCntReg;
master_2.data_array[1] = CurRxAddr;
master_2.data_array[2] = 32'h11110040 >> 2;
master_2.data_array[3] = DMACtrlReg;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;
master_2.be_array[3] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,4,1,1,1'b0); 
//Wait for Master DMA to complete
for (i = 0; i < 20; i = i + 1) begin
	repeat (20) @(posedge CLK);
	master_2.target_access(32'h2200010C,64'h0,MEM_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
	if (master_2.data_read[25:24] == 2'b00) begin
		$display("\tMaster DMA Completed Successfully");
		i = 300;
		end
	if (master_2.data_read[25:24] == 2'b10) begin
		$display("\tMaster DMA did not complete");
		i = 300;
		end
	end
if (i < 300) $display("\tMaster DMA did not complete (DMA Timeout)");



$display("\tMemory Read Multiple, %d",$time);
// Memory Read Multiple, transfer 16 doublewords
CurRxSize = 32'h10;
CurTxSize = CurRxSize;
LastDMASize = CurRxSize + CurTxSize;
// master read command 3'b110, all byte lanes on, store data in FIFO
DMACtrlReg = {8'b01_1110_01,24'h0};
DMARxTxCntReg = {CurTxSize, CurRxSize};

// write the DMA setup data to the DMA control registers in the master
master_2.data_array[0] = DMARxTxCntReg;
master_2.data_array[1] = CurRxAddr;
master_2.data_array[2] = 32'h11110080 >> 2;
master_2.data_array[3] = DMACtrlReg;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;
master_2.be_array[3] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,4,1,1,1'b0); 
//Wait for Master DMA to complete
for (i = 0; i < 20; i = i + 1) begin
	repeat (20) @(posedge CLK);
	master_2.target_access(32'h2200010C,64'h0,MEM_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
	if (master_2.data_read[25:24] == 2'b00) begin
		$display("\tMaster DMA Completed Successfully");
		i = 300;
		end
	if (master_2.data_read[25:24] == 2'b10) begin
		$display("\tMaster DMA did not complete");
		i = 300;
		end
	end
if (i < 300) $display("\tMaster DMA did not complete (DMA Timeout)");



$display("\tMemory Write, %d",$time);
// Memory Write, transfer 16 doublewords
CurRxSize = 32'h10;
CurTxSize = CurRxSize;
LastDMASize = CurRxSize + CurTxSize;
// master write command 3'b011, all byte lanes on, write data from FIFO
DMACtrlReg = {8'h40,8'h0,8'b00_0_000_01,8'h0};
DMARxTxCntReg = {CurTxSize, CurRxSize};

// write the DMA setup data to the DMA control registers in the master
master_2.data_array[0] = DMARxTxCntReg;
master_2.data_array[1] = 32'h11118000 >> 2;
master_2.data_array[2] = 32'h11110000 >> 2;
master_2.data_array[3] = DMACtrlReg;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;
master_2.be_array[3] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,4,1,1,1'b0); 
//Wait for Master DMA to complete
for (i = 0; i < 20; i = i + 1) begin
	repeat (20) @(posedge CLK);
	master_2.target_access(32'h2200010C,64'h0,MEM_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
	if (master_2.data_read[9:8] == 2'b00) begin
		$display("\tMaster DMA Completed Successfully");
		i = 300;
		end
	if (master_2.data_read[9:8] == 2'b10) begin
		$display("\tMaster DMA did not complete");
		i = 300;
		end
	end
if (i < 300) $display("\tMaster DMA did not complete (DMA Timeout)");



$display("\tMemory Write and Invalidate, %d",$time);
// Memory Write and Invalidate, transfer 16 doublewords
CurRxSize = 32'h10;
CurTxSize = CurRxSize;
LastDMASize = CurRxSize + CurTxSize;
// master write command 3'b111, all byte lanes on, write data from FIFO
DMACtrlReg = {8'h40,8'h0,8'b00_0_111_01,8'h0};
DMARxTxCntReg = {CurTxSize, CurRxSize};

// write the DMA setup data to the DMA control registers in the master
master_2.data_array[0] = DMARxTxCntReg;
master_2.data_array[1] = 32'h11118040 >> 2;
master_2.data_array[2] = 32'h11110000 >> 2;
master_2.data_array[3] = DMACtrlReg;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;
master_2.be_array[3] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,4,1,1,1'b0); 
//Wait for Master DMA to complete
for (i = 0; i < 20; i = i + 1) begin
	repeat (20) @(posedge CLK);
	master_2.target_access(32'h2200010C,64'h0,MEM_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
	if (master_2.data_read[9:8] == 2'b00) begin
		$display("\tMaster DMA Completed Successfully");
		i = 300;
		end
	if (master_2.data_read[9:8] == 2'b10) begin
		$display("\tMaster DMA did not complete");
		i = 300;
		end
	end
if (i < 300) $display("\tMaster DMA did not complete (DMA Timeout)");



$display("\tMemory Write and Invalidate with enable bit disabled (should use MW instead), %d",$time);
// Memory Write and Invalidate, transfer 16 doublewords
// disable the MWI enable bit in configuration
// master module should use Memory Write instead
// clear the MWI enable bit
repeat (5) @(posedge CLK);
master_2.target_access(32'h4,64'hFFFF0146,CONFIG_WRITE,8'hFF,0,0,1,1,1,0);

// set up the master write
CurRxSize = 32'h10;
CurTxSize = CurRxSize;
LastDMASize = CurRxSize + CurTxSize;
// master write command 3'b111, all byte lanes on, write data from FIFO
DMACtrlReg = {8'h40,8'h0,8'b00_0_111_01,8'h0};
DMARxTxCntReg = {CurTxSize, CurRxSize};

// write the DMA setup data to the DMA control registers in the master
master_2.data_array[0] = DMARxTxCntReg;
master_2.data_array[1] = 32'h11118080 >> 2;
master_2.data_array[2] = 32'h11110000 >> 2;
master_2.data_array[3] = DMACtrlReg;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;
master_2.be_array[3] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,4,1,1,1'b0); 
//Wait for Master DMA to complete
for (i = 0; i < 20; i = i + 1) begin
	repeat (20) @(posedge CLK);
	master_2.target_access(32'h2200010C,64'h0,MEM_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
	if (master_2.data_read[9:8] == 2'b00) begin
		$display("\tMaster DMA Completed Successfully");
		i = 300;
		end
	if (master_2.data_read[9:8] == 2'b10) begin
		$display("\tMaster DMA did not complete");
		i = 300;
		end
	end
if (i < 300) $display("\tMaster DMA did not complete (DMA Timeout)");

// set the MWI enable bit
repeat (5) @(posedge CLK);
master_2.target_access(32'h4,64'hFFFF0146,CONFIG_WRITE,8'hFF,0,0,1,1,1,0);

for (i = 0; i < 32'h30; i = i + 1) begin
	master_2.data_array[i] = 32'h80018001 + i;
	master_2.be_array[i] = 4'hF;
end

$display("\tVerifying data");
repeat (5) @(posedge CLK);
master_2.target_access_pf(32'h11118000,32'h00000007,MEM_READ,8'hFF,0,0,48,1,1,0, pass, 0); 
repeat (5) @(posedge CLK);

$display("\tPCI command test Completed !  %d\n",$time);
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💿 文件大小 1956 K
👤 上传用户 jessica12332145
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#VHDLVERILOG #CARDBUS #语言 #源码
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