cardbus_5632.qdf

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

  gate I249.BAR5_Hit_164 master Q_AND4I3 end
  gate I249.un2_BAR5_Hit_int_0.N_60_i master Q_XOR2I0 end
  gate I249.un2_BAR5_Hit_int_0.N_93_i master Q_XOR2I0 end
  gate I249.un2_BAR5_Hit_int_0.I_59 master Q_XOR2I0 end
  gate I249.BAR5_Hit_163 master Q_AND3I3 end
  gate I249.BAR5_Hit_172 master Q_AND3I0 end
  gate I249.un2_BAR5_Hit_int_0.N_390_i master Q_XNOR2I0 end
  gate I249.un2_BAR5_Hit_int_0.N_358_i master Q_XNOR2I0 end
  gate I249.un2_BAR5_Hit_int_0.I_399 master Q_XOR2I0 end
  gate I249.BAR5_Hit_168 master Q_AND4I1 end
  gate I249.un2_BAR5_Hit_int_0.N_324_i master Q_XNOR2I0 end
  gate I249.un2_BAR5_Hit_int_0.N_292_i master Q_XOR2I0 end
  gate I249.un2_BAR5_Hit_int_0.N_357_i master Q_XOR2I0 end
  gate I249.un2_BAR5_Hit_int_0.I_331 master Q_XOR2I0 end
  gate I249.BAR5_Hit_167 master Q_AND4I3 end
  gate I249.BAR5_Hit master Q_AND3I0 end
  gate I249.un2_BAR0_Hit_int_0.N_192_i master Q_XOR2I0 end
  gate I249.un2_BAR0_Hit_int_0.I_161 master Q_XOR2I0 end
  gate I249.BAR0_Hit_133 master Q_AND2I2 end
  gate I249.un2_BAR0_Hit_int_0.N_225_i master Q_XOR2I0 end
  gate I249.un2_BAR0_Hit_int_0.I_195 master Q_XOR2I0 end
  gate I249.BAR0_Hit_132 master Q_AND2I2 end
  gate I249.un2_BAR0_Hit_int_0.N_258_i master Q_XNOR2I0 end
  gate I249.un2_BAR0_Hit_int_0.N_226_i master Q_XOR2I0 end
  gate I249.un2_BAR0_Hit_int_0.N_291_i master Q_XOR2I0 end
  gate I249.un2_BAR0_Hit_int_0.N_259_i master Q_XOR2I0 end
  gate I249.BAR0_Hit_144 master Q_AND6I3 end
  gate I249.un2_BAR0_Hit_int_0.N_126_i master Q_XNOR2I0 end
  gate I249.un2_BAR0_Hit_int_0.N_94_i master Q_XOR2I0 end
  gate I249.un2_BAR0_Hit_int_0.N_159_i master Q_XOR2I0 end
  gate I249.un2_BAR0_Hit_int_0.I_127 master Q_XOR2I0 end
  gate I249.BAR0_Hit_138 master Q_AND4I3 end
  gate I249.un2_BAR0_Hit_int_0.N_60_i master Q_XOR2I0 end
  gate I249.un2_BAR0_Hit_int_0.N_93_i master Q_XOR2I0 end
  gate I249.un2_BAR0_Hit_int_0.I_59 master Q_XOR2I0 end
  gate I249.BAR0_Hit_137 master Q_AND3I3 end
  gate I249.BAR0_Hit_146 master Q_AND3I0 end
  gate I249.un2_BAR0_Hit_int_0.N_390_i master Q_XNOR2I0 end
  gate I249.un2_BAR0_Hit_int_0.N_358_i master Q_XNOR2I0 end
  gate I249.un2_BAR0_Hit_int_0.I_399 master Q_XOR2I0 end
  gate I249.BAR0_Hit_142 master Q_AND4I1 end
  gate I249.un2_BAR0_Hit_int_0.N_324_i master Q_XNOR2I0 end
  gate I249.un2_BAR0_Hit_int_0.N_292_i master Q_XOR2I0 end
  gate I249.un2_BAR0_Hit_int_0.N_357_i master Q_XOR2I0 end
  gate I249.un2_BAR0_Hit_int_0.I_331 master Q_XOR2I0 end
  gate I249.BAR0_Hit_141 master Q_AND4I3 end
  gate I249.BAR0_Hit master Q_AND3I0 end
  gate I249.Addr_Hit master Q_OR2I0 end
  gate I249.Usr_RdCmd master Q_OR2I0 end
  gate I249.Usr_WrCmd master Q_AND3I0 end
  gate DMA.Mst_BE_0[0] master Q_MUX2X3 end
  gate DMA.G_309 master Q_OR2I0 end
  gate DMA.Mst_BE[0] master Q_MUX2X1 end
  gate DMA.Mst_BE_0[1] master Q_MUX2X3 end
  gate DMA.Mst_BE[1] master Q_MUX2X1 end
  gate DMA.Mst_BE_0[2] master Q_MUX2X3 end
  gate DMA.Mst_BE[2] master Q_MUX2X1 end
  gate DMA.Mst_BE_0[3] master Q_MUX2X3 end
  gate DMA.Mst_BE[3] master Q_MUX2X1 end
  gate DMA.G_338 master Q_MUX2X0 end
  gate DMA.G_106_72 master Q_AND2I2 end
  gate DMA.G_106 master Q_OR5I1 end
  gate DMA.Mst_Two_Reads_0_0 master Q_OR2I0 end
  gate DMA.G_310 master Q_OR2I0 end
  gate DMA.G_296 master Q_AND2I0 end
  gate DMA.G_304 master Q_AND2I1 end
  gate DMA.G_334 master Q_AND2I2 end
  gate DMA.PCI_Cmd_1_0_iv_0_0_and2[3] master Q_AND2I1 end
  gate DMA.PCI_Cmd_1_0_iv_0_0_and2_0[3] master Q_AND2I0 end
  gate DMA.PCI_Cmd_1_0_iv_0_0[3] master Q_OR2I0 end
  gate DMA.MstWrAd_Sel_249 master Q_AND2I0 end
  gate DMA.MstWrAd_Sel master Q_AND3I0 end
  gate I_137.G_78 master Q_AND3I3 end
  gate I_137.Usr_Rdy_0_and3 master Q_AND2I0 end
  gate I222.G_70 master Q_AND2I0 end
  gate I222.un1_event_reg_cs_4_0_and2_2 master Q_AND2I0 end
  gate I222.cstschg_regs_out_0_i_and2[7] master Q_AND3I0 end
  gate DMA.Usr_RdData_0[31] master Q_MUX2X3 end
  gate I_137.dataout_1_i[31] master Q_AND2I1 end
  gate DMA.Usr_RdData_sn.G_23_0_and2 master Q_AND3I0 end
  gate DMA.Usr_RdData_1[31] master Q_MUX2X0 end
  gate DMA.Usr_RdData[31] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[30] master Q_MUX2X3 end
  gate I_137.dataout_1_i[30] master Q_AND2I1 end
  gate DMA.Usr_RdData_1[30] master Q_MUX2X0 end
  gate DMA.Usr_RdData[30] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[29] master Q_MUX2X3 end
  gate I_137.dataout_1_i[29] master Q_AND2I1 end
  gate DMA.Usr_RdData_1[29] master Q_MUX2X0 end
  gate DMA.Usr_RdData[29] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[28] master Q_MUX2X3 end
  gate I_137.dataout_1_i[28] master Q_AND2I1 end
  gate DMA.Usr_RdData_1[28] master Q_MUX2X0 end
  gate DMA.Usr_RdData[28] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[27] master Q_MUX2X3 end
  gate I_137.dataout_1_i[27] master Q_AND2I1 end
  gate DMA.Usr_RdData_1[27] master Q_MUX2X0 end
  gate DMA.Usr_RdData[27] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[26] master Q_MUX2X3 end
  gate I_137.G_95 master Q_OR2I0 end
  gate I_137.G_107 master Q_MUX2X3 end
  gate I_137.dataout_1_0_iv_i[26] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[26] master Q_MUX2X0 end
  gate DMA.Usr_RdData[26] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[25] master Q_MUX2X3 end
  gate I_137.G_106 master Q_MUX2X3 end
  gate I_137.dataout_1_0_iv_i[25] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[25] master Q_MUX2X0 end
  gate DMA.Usr_RdData[25] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[24] master Q_MUX2X3 end
  gate I_137.G_105 master Q_MUX2X3 end
  gate I_137.dataout_1_0_iv_i[24] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[24] master Q_MUX2X0 end
  gate DMA.Usr_RdData[24] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[23] master Q_MUX2X3 end
  gate I_137.dataout_1_i[23] master Q_AND2I1 end
  gate DMA.Usr_RdData_1[23] master Q_MUX2X0 end
  gate DMA.Usr_RdData[23] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[22] master Q_MUX2X3 end
  gate I_137.G_88 master Q_XOR2I0 end
  gate I_137.dataout_1[22] master Q_MUX2X3 end
  gate DMA.Usr_RdData_1[22] master Q_MUX2X1 end
  gate DMA.Usr_RdData[22] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[21] master Q_MUX2X3 end
  gate I_137.dataout_1[21] master Q_MUX2X3 end
  gate DMA.Usr_RdData_1[21] master Q_MUX2X1 end
  gate DMA.Usr_RdData[21] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[20] master Q_MUX2X3 end
  gate I_137.dataout_1[20] master Q_MUX2X3 end
  gate DMA.Usr_RdData_1[20] master Q_MUX2X1 end
  gate DMA.Usr_RdData[20] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[19] master Q_MUX2X3 end
  gate I_137.dataout_1_1[19] master Q_MUX2X3 end
  gate I_137.dataout_1_i[19] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[19] master Q_MUX2X0 end
  gate DMA.Usr_RdData[19] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[18] master Q_MUX2X3 end
  gate I_137.dataout_1_1[18] master Q_MUX2X0 end
  gate I_137.dataout_1[18] master Q_MUX2X3 end
  gate DMA.Usr_RdData_1[18] master Q_MUX2X1 end
  gate DMA.Usr_RdData[18] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[17] master Q_MUX2X3 end
  gate I_137.dataout_1_1[17] master Q_MUX2X0 end
  gate I_137.dataout_1[17] master Q_MUX2X3 end
  gate DMA.Usr_RdData_1[17] master Q_MUX2X1 end
  gate DMA.Usr_RdData[17] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[16] master Q_MUX2X3 end
  gate I_137.dataout_1_1[16] master Q_MUX2X0 end
  gate I_137.dataout_1[16] master Q_MUX2X3 end
  gate DMA.Usr_RdData_1[16] master Q_MUX2X1 end
  gate DMA.Usr_RdData[16] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[15] master Q_MUX2X3 end
  gate I_137.dataout_1_1[15] master Q_MUX2X3 end
  gate I_137.dataout_1_i[15] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[15] master Q_MUX2X0 end
  gate DMA.Usr_RdData[15] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[14] master Q_MUX2X3 end
  gate I_137.dataout_1_1[14] master Q_MUX2X3 end
  gate I_137.dataout_1_i[14] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[14] master Q_MUX2X0 end
  gate DMA.Usr_RdData[14] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[13] master Q_MUX2X3 end
  gate I_137.dataout_1_1[13] master Q_MUX2X3 end
  gate I_137.dataout_1_i[13] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[13] master Q_MUX2X0 end
  gate DMA.Usr_RdData[13] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[12] master Q_MUX2X3 end
  gate I_137.dataout_1_1[12] master Q_MUX2X3 end
  gate I_137.dataout_1_i[12] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[12] master Q_MUX2X0 end
  gate DMA.Usr_RdData[12] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[11] master Q_MUX2X3 end
  gate I_137.dataout_1_1[11] master Q_MUX2X3 end
  gate I_137.dataout_1_i[11] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[11] master Q_MUX2X0 end
  gate DMA.Usr_RdData[11] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[10] master Q_MUX2X3 end
  gate I_137.dataout_1_1[10] master Q_MUX2X3 end
  gate I_137.dataout_1_i[10] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[10] master Q_MUX2X0 end
  gate DMA.Usr_RdData[10] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[9] master Q_MUX2X3 end
  gate I_137.dataout_1_1[9] master Q_MUX2X3 end
  gate I_137.dataout_1_i[9] master Q_AND2I2 end
  gate DMA.Usr_RdData_1[9] master Q_MUX2X0 end
  gate DMA.Usr_RdData[9] master Q_MUX2X2 end
  gate DMA.Usr_RdData_0[8] master Q_MUX2X3 end
  gate I_137.dataout_1_1[8] master Q_MUX2X0 end
  gate I_137.dataout_1[8] master Q_MUX2X3 end
  gate DMA.Usr_RdData_1[8] master Q_MUX2X1 end
  gate DMA.Usr_RdData[8] master Q_MUX2X2 end
  gate I_137.dataout_1_1[7] master Q_MUX2X3 end
  gate I_137.dataout_1[7] master Q_MUX2X1 end
  gate DMA.Usr_RdData_1[7] master Q_MUX2X3 end
  gate DMA.Usr_RdData[7] master Q_MUX2X1 end
  gate I_137.dataout_1_1[6] master Q_MUX2X3 end
  gate I_137.dataout_1[6] master Q_MUX2X1 end
  gate DMA.Usr_RdData_1[6] master Q_MUX2X3 end
  gate DMA.Usr_RdData[6] master Q_MUX2X1 end
  gate I_137.dataout_1_1[5] master Q_MUX2X3 end
  gate I_137.dataout_1[5] master Q_MUX2X1 end
  gate DMA.Usr_RdData_1[5] master Q_MUX2X3 end
  gate DMA.Usr_RdData[5] master Q_MUX2X1 end
  gate I_137.dataout_1_1[4] master Q_MUX2X3 end
  gate I_137.dataout_1[4] master Q_MUX2X1 end
  gate DMA.Usr_RdData_1[4] master Q_MUX2X3 end
  gate DMA.Usr_RdData[4] master Q_MUX2X1 end
  gate I_137.dataout_1_1[3] master Q_MUX2X3 end
  gate I_137.dataout_1[3] master Q_MUX2X1 end
  gate DMA.Usr_RdData_1[3] master Q_MUX2X3 end
  gate DMA.Usr_RdData[3] master Q_MUX2X1 end
  gate I_137.dataout_1_0[2] master Q_MUX2X3 end
  gate I_137.dataout_1_1[2] master Q_MUX2X0 end
  gate I_137.dataout_1[2] master Q_MUX2X2 end
  gate DMA.Usr_RdData_1[2] master Q_MUX2X3 end
  gate DMA.Usr_RdData[2] master Q_MUX2X1 end
  gate I_137.dataout_1_0[1] master Q_MUX2X3 end
  gate I_137.dataout_1_1[1] master Q_MUX2X0 end
  gate I_137.dataout_1[1] master Q_MUX2X2 end
  gate DMA.Usr_RdData_1[1] master Q_MUX2X3 end
  gate DMA.Usr_RdData[1] master Q_MUX2X1 end
  gate I_137.dataout_1_0[0] master Q_MUX2X3 end
  gate I_137.dataout_1_1[0] master Q_MUX2X0 end
  gate I_137.dataout_1[0] master Q_MUX2X2 end
  gate DMA.Usr_RdData_1[0] master Q_MUX2X3 end
  gate DMA.Usr_RdData[0] master Q_MUX2X1 end
  gate I222.CCLKRUN_n_oe_0_and2 master Q_AND2I0 end
  gate I222.un1_CINT_n_i_0 master Q_OR2I1 end
  gate I222.CSTSCHG_0_and2_2 master Q_AND3I0 end
  gate I222.CSTSCHG_0_and2_1 master Q_AND3I0 end
  gate I222.CSTSCHG_0_and2_0 master Q_AND3I0 end
  gate I222.G_85 master Q_OR2I0 end
  gate I222.CSTSCHG_0_and2_106 master Q_AND2I0 end
  gate I222.CSTSCHG_0_and2 master Q_AND3I0 end
  gate I222.CSTSCHG_0 master Q_OR4I0 end
  gate I222.CAUDIO_0 master Q_MUX2X3 end
  gate I222.G_84 master Q_XNOR2I0 end
  gate I222.CAUDIO_1_and2 master Q_AND2I2 end
  gate DMA.G_339 master Q_MUX2X0 end
  gate I250.un1_last_cycle_0 master Q_OR2I0 end
  gate I250.CIS_Hit_0 master Q_MUX2X0 end
  gate DMA.BEfifo23_0_and2 master Q_AND2I0 end
  gate DMA.WrDMACnt_254 master Q_AND3I0 end
  gate DMA.Dec_BCnt_0_0_and2_0 master Q_AND2I0 end
  gate DMA.Dec_BCnt_0_0 master Q_OR2I0 end
  gate DMA.G_297 master Q_AND3I0 end
  gate DMA.Mst_WrBE_8[2] master Q_MUX2X0 end
  gate DMA.Mst_WrBE_8[3] master Q_MUX2X0 end
  gate DMA.Mst_WrBE_9[0] master Q_MUX2X0 end
  gate DMA.Mst_WrBE_9[1] master Q_MUX2X0 end
  gate DMA.G_319 master Q_OR2I0 end
  gate DMA.BCnt2_eq_1_67 master Q_AND2I2 end
  gate DMA.BCnt2_eq_1_66 master Q_AND2I2 end
  gate DMA.BCnt2_eq_1 master Q_AND6I3 end
  gate DMA.StateEqns.Mst_RdBE_Load_Done_11_iv_0_0_and2_0 master Q_AND3I0 end
  gate DMA.StateEqns.Mst_RdBE_Load_Done_11_iv_0_0 master Q_AND2I2 end
  gate DMA.Mst_RdBE_Load_Done_0 master Q_MUX2X2 end
  gate DMA.un1_Mst_Tabort_Det master Q_OR2I0 end
  gate DMA.un1_Mst_WrBE_Sel7_1_i_or2_0_and2 master Q_AND2I0 end
  gate DMA.G_287 master Q_AND3I0 end
  gate DMA.DMAWrEn_11_i_0_or2 master Q_OR2I0 end
  gate DMA.un1_DMAWrEn22_2_i_0 master Q_OR2I0 end
  gate DMA.DMAWrEn_0 master Q_MUX2X0 end
  gate DMA.un1_Mst_LatCntEn7_1_i_or2_0_and2 master Q_AND2I0 end
  gate DMA.G_288 master Q_AND2I0 end
  gate DMA.DMARdEn_11_i_0_or2 master Q_OR2I0 end
  gate DMA.un1_DMARdEn22_2_i_0 master Q_OR2I0 end
  gate DMA.DMARdEn_0 master Q_MUX2X0 end
  gate DMA.Mst_WrData_Valid_14_i_0_and2 master Q_AND3I0 end
  gate DMA.Mst_WrData_Valid_14_i_0_and2_0 master Q_AND3I0 end
  gate DMA.Mst_WrData_Valid_14_i_0 master Q_AND2I2 end
  gate DMA.un1_un37_Mst_WrData_Valid_1_0_mux2_i master Q_OR2I0 end
  gate DMA.Mst_WrData_Valid_0 master Q_MUX2X0 end
  gate DMA.DMAWrErr_8_i_and2_i master Q_AND2I2 end
  gate DMA.un1_Mst_WrBE_Sel7_1_i_or2_0 master Q_OR2I0 end
  gate DMA.DMAWrErr_0 master Q_MUX2X2 end
  gate DMA.DMARdErr_8_i_and2_i master Q_AND2I2 end
  gate DMA.un1_Mst_LatCntEn7_1_i_or2_0 master Q_OR2I0 end
  gate DMA.DMARdErr_0 master Q_MUX2X2 end
  gate DMA.Mst_RdCmd_0[0] master Q_MUX2X0 end
  gate DMA.Mst_RdCmd_0[1] master Q_MUX2X0 end
  gate DMA.Mst_RdCmd_0[2] master Q_MUX2X0 end
  gate DMA.Mst_RdCmd_0[3] master Q_MUX2X0 end
  gate DMA.Mst_RdBE_0[0] master Q_MUX2X0 end
  gate DMA.Mst_RdBE_0[1] master Q_MUX2X0 end
  gate DMA.Mst_RdBE_0[2] master Q_MUX2X0 end
  gate DMA.Mst_RdBE_0[3] master Q_MUX2X0 end
  gate DMA.Mst_WrCmd_0[0] master Q_MUX2X0 end
  gate DMA.Mst_WrCmd_0[1] master Q_MUX2X0 end
  gate DMA.Mst_WrCmd_0[2] master Q_MUX2X0 end
  gate DMA.Mst_WrData_Sel_0 master Q_MUX2X0 end
  gate DMA.Mst_WrBE_Sel_0 master Q_MUX2X0 end
  gate DMA.Mst_Rd_Term_Sel_0 master Q_MUX2X0 end
  gate DMA.Mst_RdData_Sel_0 master Q_MUX2X0 end
  gate DMA.Mst_RdBE_Sel_0 master Q_MUX2X0 end
  gate DMA.Mst_LatCntEn_0 master Q_MUX2X0 end
  gate DMA.LocalEn_0 master Q_MUX2X0 end
  gate DMA.Mst_D_Reg6_0_0_and2 master Q_AND2I0 end
  gate DMA.Mst_D_Reg6_0_0_and2_0 master Q_AND2I0 end
  gate DMA.Mst_D_Reg6_0_0 master Q_OR2I0 end
  gate DMA.WD_Reg_0[0] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[1] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[2] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[3] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[4] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[5] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[6] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[7] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[8] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[9] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[10] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[11] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[12] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[13] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[14] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[15] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[16] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[17] master Q_MUX2X0 end
  gate DMA.WD_Reg_0[18] master Q_MUX2X