cardbus_5632.qdf

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

  gate I_137.target_ram3.r128a8I1 master RAM128X9 end
  gate I_137.target_ram2.r128a8I1 master RAM128X9 end
  gate I_137.target_ram1.r128a8I1 master RAM128X9 end
  gate I_137.target_ram0.r128a8I1 master RAM128X9 end
  gate I_137.I_1 master Q_DECX end
  gate I_137.I_2 master Q_DECX end
  gate I_137.I_3 master Q_DECX end
  gate I_137.un1_WaitCount_1.CO1 master Q_AND2 end
  gate I_137.un1_WaitCount_1.SUM0 master Q_INCX end
  gate I_137.un1_WaitCount_1.SUM1 master Q_INCX end
  gate I_137.un1_WaitCount_1.SUM2 master Q_INCX end
  gate I_137.un1_perfcount_1.CO6 master Q_INCSKIP2 pack end
  gate I_137.un1_perfcount_1.CO12 master Q_INCSKIP2 pack end
  gate I_137.un1_perfcount_1.CO18 master Q_INCSKIP2 pack end
  gate I_137.un1_perfcount_1.CO1 master Q_AND2 end
  gate I_137.un1_perfcount_1.CO2 master Q_AND2 end
  gate I_137.un1_perfcount_1.CO4 master Q_AND2 end
  gate I_137.un1_perfcount_1.CO5 master Q_AND2 end
  gate I_137.un1_perfcount_1.CO7 master Q_AND2 end
  gate I_137.un1_perfcount_1.CO8 master Q_AND2 end
  gate I_137.un1_perfcount_1.CO10 master Q_AND2 end
  gate I_137.un1_perfcount_1.CO11 master Q_AND2 end
  gate I_137.un1_perfcount_1.CO13 master Q_AND2 end
  gate I_137.un1_perfcount_1.CO14 master Q_AND2 end
  gate I_137.un1_perfcount_1.CO16 master Q_AND2 end
  gate I_137.un1_perfcount_1.CO17 master Q_AND2 end
  gate I_137.un1_perfcount_1.SUM0 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM1 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM2 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM3 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM4 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM5 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM6 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM7 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM8 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM9 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM10 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM11 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM12 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM13 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM14 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM15 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM16 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM17 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM18 master Q_INCX end
  gate I_137.un1_perfcount_1.SUM19 master Q_INCX end
  gate I_137.un1_StopCount_1.CO1 master Q_AND2 end
  gate I_137.un1_StopCount_1.SUM0 master Q_INCX end
  gate I_137.un1_StopCount_1.SUM1 master Q_INCX end
  gate I_137.un1_StopCount_1.SUM2 master Q_INCX end
  gate WrBuff.I_120 master dffpa end
  gate WrBuff.I_45 master or2i0 end
  gate WrBuff.I_50 master and2i1 end
  gate WrBuff.I_69 master and2i1 end
  gate WrBuff.I_17.I_11 master and3i1 end
  gate WrBuff.I_17.I_12 master xor2i0 end
  gate WrBuff.I_17.I_10.I_2 master LOGIC2 end
  gate WrBuff.I_17.I_9.I_2 master LOGIC2 end
  gate WrBuff.I_18.I_11 master and3i1 end
  gate WrBuff.I_18.I_12 master xor2i0 end
  gate WrBuff.I_18.I_10.I_2 master LOGIC2 end
  gate WrBuff.I_18.I_9.I_2 master LOGIC2 end
  gate WrBuff.I_85.I_11 master and3i1 end
  gate WrBuff.I_85.I_12 master xor2i0 end
  gate WrBuff.I_85.I_10.I_2 master LOGIC2 end
  gate WrBuff.I_85.I_9.I_2 master LOGIC2 end
  gate WrBuff.I_19.I_11 master and3i1 end
  gate WrBuff.I_19.I_12 master xor2i0 end
  gate WrBuff.I_19.I_10.I_2 master LOGIC2 end
  gate WrBuff.I_19.I_9.I_2 master LOGIC2 end
  gate WrBuff.I_26.I_11 master and3i1 end
  gate WrBuff.I_26.I_12 master xor2i0 end
  gate WrBuff.I_26.I_10.I_2 master LOGIC2 end
  gate WrBuff.I_26.I_9.I_2 master LOGIC2 end
  gate WrBuff.I136.I26 master or2i0 end
  gate WrBuff.I136.I23 master and3i3 end
  gate WrBuff.I136.I15 master and2i2 end
  gate WrBuff.I136.I16 master mux2x2 end
  gate WrBuff.I136.I17 master mux2x2 end
  gate WrBuff.I136.I19 master Q_AND2I0 end
  gate WrBuff.I136.I24 master Q_AND2I0 end
  gate WrBuff.I136.I20 master Q_AND2I0 end
  gate WrBuff.I136.I21 master dffpc end
  gate WrBuff.I136.I22 master dffpc end
  gate WrBuff.I136.I25 master dff end
  gate WrBuff.I136.I13 master dff end
  gate WrBuff.I135.I26 master or2i0 end
  gate WrBuff.I135.I23 master and3i3 end
  gate WrBuff.I135.I15 master and2i2 end
  gate WrBuff.I135.I16 master mux2x2 end
  gate WrBuff.I135.I17 master mux2x2 end
  gate WrBuff.I135.I19 master Q_AND2I0 end
  gate WrBuff.I135.I24 master Q_AND2I0 end
  gate WrBuff.I135.I20 master Q_AND2I0 end
  gate WrBuff.I135.I21 master dffpc end
  gate WrBuff.I135.I22 master dffpc end
  gate WrBuff.I135.I25 master dff end
  gate WrBuff.I135.I13 master dff end
  gate WrBuff.I137.r128x32_25umI1 master RAM128X18_25UM end
  gate WrBuff.I137.r128x32_25umI2 master RAM128X18_25UM end
  gate Rdbuff.I_120 master dffpa end
  gate Rdbuff.I_45 master or2i0 end
  gate Rdbuff.I_50 master and2i1 end
  gate Rdbuff.I_69 master and2i1 end
  gate Rdbuff.I_17.I_11 master and3i1 end
  gate Rdbuff.I_17.I_12 master xor2i0 end
  gate Rdbuff.I_17.I_10.I_2 master LOGIC2 end
  gate Rdbuff.I_17.I_9.I_2 master LOGIC2 end
  gate Rdbuff.I_18.I_11 master and3i1 end
  gate Rdbuff.I_18.I_12 master xor2i0 end
  gate Rdbuff.I_18.I_10.I_2 master LOGIC2 end
  gate Rdbuff.I_18.I_9.I_2 master LOGIC2 end
  gate Rdbuff.I_85.I_11 master and3i1 end
  gate Rdbuff.I_85.I_12 master xor2i0 end
  gate Rdbuff.I_85.I_10.I_2 master LOGIC2 end
  gate Rdbuff.I_85.I_9.I_2 master LOGIC2 end
  gate Rdbuff.I_19.I_11 master and3i1 end
  gate Rdbuff.I_19.I_12 master xor2i0 end
  gate Rdbuff.I_19.I_10.I_2 master LOGIC2 end
  gate Rdbuff.I_19.I_9.I_2 master LOGIC2 end
  gate Rdbuff.I_26.I_11 master and3i1 end
  gate Rdbuff.I_26.I_12 master xor2i0 end
  gate Rdbuff.I_26.I_10.I_2 master LOGIC2 end
  gate Rdbuff.I_26.I_9.I_2 master LOGIC2 end
  gate Rdbuff.I136.I26 master or2i0 end
  gate Rdbuff.I136.I23 master and3i3 end
  gate Rdbuff.I136.I15 master and2i2 end
  gate Rdbuff.I136.I16 master mux2x2 end
  gate Rdbuff.I136.I17 master mux2x2 end
  gate Rdbuff.I136.I19 master Q_AND2I0 end
  gate Rdbuff.I136.I24 master Q_AND2I0 end
  gate Rdbuff.I136.I20 master Q_AND2I0 end
  gate Rdbuff.I136.I21 master dffpc end
  gate Rdbuff.I136.I22 master dffpc end
  gate Rdbuff.I136.I25 master dff end
  gate Rdbuff.I136.I13 master dff end
  gate Rdbuff.I135.I26 master or2i0 end
  gate Rdbuff.I135.I23 master and3i3 end
  gate Rdbuff.I135.I15 master and2i2 end
  gate Rdbuff.I135.I16 master mux2x2 end
  gate Rdbuff.I135.I17 master mux2x2 end
  gate Rdbuff.I135.I24 master Q_AND2I0 end
  gate Rdbuff.I135.I21 master dffpc end
  gate Rdbuff.I135.I22 master dffpc end
  gate Rdbuff.I135.I25 master dff end
  gate Rdbuff.I135.I13 master dff end
  gate Rdbuff.I137.r128x32_25umI1 master RAM128X18_25UM end
  gate Rdbuff.I137.r128x32_25umI2 master RAM128X18_25UM end
  gate I249.un6_UsrAddr_1.CO6 master Q_INCSKIP2 pack end
  gate I249.un6_UsrAddr_1.CO1 master Q_AND2 end
  gate I249.un6_UsrAddr_1.CO2 master Q_AND2 end
  gate I249.un6_UsrAddr_1.CO4 master Q_AND2 end
  gate I249.un6_UsrAddr_1.CO5 master Q_AND2 end
  gate I249.un6_UsrAddr_1.SUM1 master Q_INCX end
  gate I249.un6_UsrAddr_1.SUM2 master Q_INCX end
  gate I249.un6_UsrAddr_1.SUM3 master Q_INCX end
  gate I249.un6_UsrAddr_1.SUM4 master Q_INCX end
  gate I249.un6_UsrAddr_1.SUM5 master Q_INCX end
  gate I249.un6_UsrAddr_1.SUM6 master Q_INCX end
  gate I249.un6_UsrAddr_1.SUM7 master Q_INCX end
  gate I251.r64x4I1.r64x4I1 master RAM64X18 end
  gate I251.ucnt6I1.q_5_1.CO3 master Q_INCSKIP pack end
  gate I251.ucnt6I1.q_5_1.CO1 master Q_AND2 end
  gate I251.ucnt6I1.q_5_1.CO2 master Q_AND2 end
  gate I251.ucnt6I1.q_5_1.CO4 master Q_AND2 end
  gate I251.ucnt6I1.q_5_1.SUM0 master Q_INCX end
  gate I251.ucnt6I1.q_5_1.SUM1 master Q_INCX end
  gate I251.ucnt6I1.q_5_1.SUM2 master Q_INCX end
  gate I251.ucnt6I1.q_5_1.SUM3 master Q_INCX end
  gate I251.ucnt6I1.q_5_1.SUM4 master Q_INCX end
  gate I251.ucnt6I1.q_5_1.SUM5 master Q_INCX end
  gate I251.ucnt6I2.q_5_1.CO3 master Q_INCSKIP pack end
  gate I251.ucnt6I2.q_5_1.CO1 master Q_AND2 end
  gate I251.ucnt6I2.q_5_1.CO2 master Q_AND2 end
  gate I251.ucnt6I2.q_5_1.CO4 master Q_AND2 end
  gate I251.ucnt6I2.q_5_1.SUM0 master Q_INCX end
  gate I251.ucnt6I2.q_5_1.SUM1 master Q_INCX end
  gate I251.ucnt6I2.q_5_1.SUM2 master Q_INCX end
  gate I251.ucnt6I2.q_5_1.SUM3 master Q_INCX end
  gate I251.ucnt6I2.q_5_1.SUM4 master Q_INCX end
  gate I251.ucnt6I2.q_5_1.SUM5 master Q_INCX end
  gate I251.G_15.I_2 master LOGIC2 end
  gate I251.G_15.I_7 master LOGIC2 end
  gate I251.G_15.I_12 master LOGIC2 end
  gate I251.G_15.I_17 master LOGIC2 end
  gate I251.G_15.I_22 master LOGIC2 end
  gate I251.G_15.I_27 master LOGIC2 end
  gate I251.G_15.I_37 master LOGIC2 end
  gate I251.G_15.I_42 master LOGIC2 end
  gate I251.G_15.I_57 master LOGIC2 end
  gate I251.G_15.I_62 master LOGIC2 end
  gate I251.G_15.I_67 master LOGIC2 end
  gate I251.G_15.I_72 master LOGIC2 end
  gate I251.G_15.I_77 master LOGIC2 end
  gate I251.G_15.I_82 master LOGIC2 end
  gate I249.G_118 master Q_AND2I0 end
  gate I249.G_121 master Q_AND2I0 end
  gate I249.CfgData23_0_and2 master Q_AND2I0 end
  gate I249.CfgData_2_1_iv_0_or2[12] master Q_OR2I0 end
  gate I249.G_123 master Q_AND2I0 end
  gate I249.MemEnable_m master Q_AND2I0 end
  gate I249.CfgData_2_1_iv[1] master Q_OR4I0 end
  gate I249.CacheLineSizeReg_m[2] master Q_AND2I0 end
  gate I249.BusMasterEnable_m master Q_AND2I0 end
  gate I249.CfgData_2_0_iv[2] master Q_OR3I0 end
  gate I249.CacheLineSizeReg_m[3] master Q_AND2I0 end
  gate I249.SpecialCycleEnable_m master Q_AND2I0 end
  gate I249.CfgData_2_0_iv[3] master Q_OR2I0 end
  gate I249.CacheLineSizeReg_m[4] master Q_AND2I0 end
  gate I249.MemWrAndInvalidateEnable_m master Q_AND2I0 end
  gate I249.CfgData_2_0_iv[4] master Q_OR2I0 end
  gate I249.CacheLineSizeReg_m[5] master Q_AND2I0 end
  gate I249.CfgData_2_1_iv[5] master Q_OR2I0 end
  gate I249.CacheLineSizeReg_m[6] master Q_AND2I0 end
  gate I249.ParityErrorEnable_m master Q_AND2I0 end
  gate I249.CfgData_2_1_iv[6] master Q_OR3I0 end
  gate I249.CacheLineSizeReg_m[7] master Q_AND2I0 end
  gate I249.CfgData_2_1_iv[7] master Q_OR2I0 end
  gate I249.LatTimerReg_m[0] master Q_AND2I0 end
  gate I249.SERREnable_m master Q_AND2I0 end
  gate I249.CfgData_2_1_iv[8] master Q_OR3I0 end
  gate I249.CfgData_1_0_and2[9] master Q_AND2I0 end
  gate I249.G_117 master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2_0[10] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2_1[10] master Q_AND2I0 end
  gate I249.G_119 master Q_AND2I0 end
  gate I249.G_120 master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2[10] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0[10] master Q_OR3I0 end
  gate I249.CfgData_2_0_iv_0_and2_0[11] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2_1[11] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2[11] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0[11] master Q_OR3I0 end
  gate I249.CfgData_2_1_iv_0_and2[12] master Q_AND2I0 end
  gate I249.CfgData_2_1_iv_0_and2_0_12_230 master Q_AND2I0 end
  gate I249.CfgData_2_1_iv_0_and2_0[12] master Q_AND3I0 end
  gate I249.CfgData_2_1_iv_0_and2_1[12] master Q_AND2I0 end
  gate I249.CfgData_2_1_iv_0[12] master Q_OR4I0 end
  gate I249.CfgData_2_0_iv_0_and2_0[13] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2_1[13] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2[13] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0[13] master Q_OR3I0 end
  gate I249.CfgData_2_0_iv_0_and2_0[14] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2_1[14] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2[14] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0[14] master Q_OR3I0 end
  gate I249.CfgData_2_0_iv_0_and2_0[15] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2_1[15] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2[15] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0[15] master Q_OR3I0 end
  gate I249.BAR0_reg_m[16] master Q_AND2I0 end
  gate I249.BAR5_reg_m[16] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv[16] master Q_OR2I0 end
  gate I249.BAR0_reg_m[17] master Q_AND2I0 end
  gate I249.BAR5_reg_m[17] master Q_AND2I0 end
  gate I249.CfgData_2_1_iv[17] master Q_OR3I0 end
  gate I249.BAR0_reg_m[18] master Q_AND2I0 end
  gate I249.BAR5_reg_m[18] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv[18] master Q_OR3I0 end
  gate I249.BAR0_reg_m[19] master Q_AND2I0 end
  gate I249.BAR5_reg_m[19] master Q_AND2I0 end
  gate I249.CfgData25_0_and2_251 master Q_AND2I0 end
  gate I249.CfgData25_0_and2 master Q_AND3I0 end
  gate I249.CfgData_2_1_iv[19] master Q_OR4I0 end
  gate I249.BAR0_reg_m[20] master Q_AND2I0 end
  gate I249.BAR5_reg_m[20] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv[20] master Q_OR3I0 end
  gate I249.CfgData_2_0_iv_0_and2[21] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2_0[21] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0[21] master Q_OR2I0 end
  gate I249.CfgData_2_0_iv_0_and2[22] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2_0[22] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0[22] master Q_OR2I0 end
  gate I249.CfgData_2_0_iv_0_and2_0[23] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2[23] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0[23] master Q_OR3I0 end
  gate I249.CfgData_2_0_iv_0_and2_2[24] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2_1[24] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2_0[24] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0[24] master Q_OR4I0 end
  gate I249.CfgData_2_0_iv_0_and2_0[25] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2[25] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0[25] master Q_OR4I0 end
  gate I249.BAR0_reg_m[26] master Q_AND2I0 end
  gate I249.BAR5_reg_m[26] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv[26] master Q_OR3I0 end
  gate I249.BAR0_reg_m[27] master Q_AND2I0 end
  gate I249.BAR5_reg_m[27] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv[27] master Q_OR3I0 end
  gate I249.BAR0_reg_m[28] master Q_OR2I2 end
  gate I249.BAR5_reg_m[28] master Q_AND2I0 end
  gate I249.ReceivedTargetAbort_m master Q_AND2I0 end
  gate I249.CfgData_2_1_iv[28] master Q_OR5I1 end
  gate I249.CfgData_2_0_iv_0_and2_1[29] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2_0[29] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2[29] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0[29] master Q_OR4I0 end
  gate I249.BAR0_reg_m[30] master Q_AND2I0 end
  gate I249.BAR5_reg_m[30] master Q_AND2I0 end
  gate I249.SignaledSystemError_m master Q_AND2I0 end
  gate I249.CfgData_2_0_iv[30] master Q_OR4I0 end
  gate I249.CfgData_2_0_iv_0_and2_1[31] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2_0[31] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0_and2[31] master Q_AND2I0 end
  gate I249.CfgData_2_0_iv_0[31] master Q_OR4I0 end
  gate I249.un2_BAR5_Hit_int_0.N_192_i master Q_XOR2I0 end
  gate I249.un2_BAR5_Hit_int_0.I_161 master Q_XOR2I0 end
  gate I249.BAR5_Hit_159 master Q_AND2I2 end
  gate I249.un2_BAR5_Hit_int_0.N_225_i master Q_XOR2I0 end
  gate I249.un2_BAR5_Hit_int_0.I_195 master Q_XOR2I0 end
  gate I249.BAR5_Hit_158 master Q_AND2I2 end
  gate I249.un2_BAR5_Hit_int_0.N_258_i master Q_XNOR2I0 end
  gate I249.un2_BAR5_Hit_int_0.N_226_i master Q_XOR2I0 end
  gate I249.un2_BAR5_Hit_int_0.N_291_i master Q_XOR2I0 end
  gate I249.un2_BAR5_Hit_int_0.N_259_i master Q_XOR2I0 end
  gate I249.BAR5_Hit_170 master Q_AND6I3 end
  gate I249.un2_BAR5_Hit_int_0.N_126_i master Q_XNOR2I0 end
  gate I249.un2_BAR5_Hit_int_0.N_94_i master Q_XOR2I0 end
  gate I249.un2_BAR5_Hit_int_0.N_159_i master Q_XOR2I0 end
  gate I249.un2_BAR5_Hit_int_0.I_127 master Q_XOR2I0 end