cardbus_5632.qdf

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

  gate CIS_data[19] master inpad_25um end
  gate CIS_data[18] master inpad_25um end
  gate CIS_data[17] master inpad_25um end
  gate CIS_data[16] master inpad_25um end
  gate CIS_data[15] master inpad_25um end
  gate CIS_data[14] master inpad_25um end
  gate CIS_data[13] master inpad_25um end
  gate CIS_data[12] master inpad_25um end
  gate CIS_data[11] master inpad_25um end
  gate CIS_data[10] master inpad_25um end
  gate CIS_data[9] master inpad_25um end
  gate CIS_data[8] master inpad_25um end
  gate CIS_data[7] master inpad_25um end
  gate CIS_data[6] master inpad_25um end
  gate CIS_data[5] master inpad_25um end
  gate CIS_data[4] master inpad_25um end
  gate CIS_data[3] master inpad_25um end
  gate CIS_data[2] master inpad_25um end
  gate CIS_data[1] master inpad_25um end
  gate CIS_data[0] master inpad_25um end
  gate I229 master bipad_25um end
  gate I170 master tripad_25um end
  gate I187 master gclkbuff_25um end
  gate I188 master gclkbuff_25um end
  gate I215 master gclkbuff_25um end
  gate ladpads[31] master bipadiff_25um end
  gate ladpads[30] master bipadiff_25um end
  gate ladpads[29] master bipadiff_25um end
  gate ladpads[28] master bipadiff_25um end
  gate ladpads[27] master bipadiff_25um end
  gate ladpads[26] master bipadiff_25um end
  gate ladpads[25] master bipadiff_25um end
  gate ladpads[24] master bipadiff_25um end
  gate ladpads[23] master bipadiff_25um end
  gate ladpads[22] master bipadiff_25um end
  gate ladpads[21] master bipadiff_25um end
  gate ladpads[20] master bipadiff_25um end
  gate ladpads[19] master bipadiff_25um end
  gate ladpads[18] master bipadiff_25um end
  gate ladpads[17] master bipadiff_25um end
  gate ladpads[16] master bipadiff_25um end
  gate ladpads[15] master bipadiff_25um end
  gate ladpads[14] master bipadiff_25um end
  gate ladpads[13] master bipadiff_25um end
  gate ladpads[12] master bipadiff_25um end
  gate ladpads[11] master bipadiff_25um end
  gate ladpads[10] master bipadiff_25um end
  gate ladpads[9] master bipadiff_25um end
  gate ladpads[8] master bipadiff_25um end
  gate ladpads[7] master bipadiff_25um end
  gate ladpads[6] master bipadiff_25um end
  gate ladpads[5] master bipadiff_25um end
  gate ladpads[4] master bipadiff_25um end
  gate ladpads[3] master bipadiff_25um end
  gate ladpads[2] master bipadiff_25um end
  gate ladpads[1] master bipadiff_25um end
  gate ladpads[0] master bipadiff_25um end
  gate I189 master ckpad_25um end
  gate I241 master outpad_25um end
  gate I242 master outpad_25um end
  gate I243 master outpad_25um end
  gate I230 master outpad_25um end
  gate I231 master outpad_25um end
  gate I232 master outpad_25um end
  gate CIS_ADR[9] master outpad_25um end
  gate CIS_ADR[8] master outpad_25um end
  gate CIS_ADR[7] master outpad_25um end
  gate CIS_ADR[6] master outpad_25um end
  gate CIS_ADR[5] master outpad_25um end
  gate CIS_ADR[4] master outpad_25um end
  gate CIS_ADR[3] master outpad_25um end
  gate CIS_ADR[2] master outpad_25um end
  gate I217 master outpad_25um end
  gate ledpads[7] master outpad_25um end
  gate ledpads[6] master outpad_25um end
  gate ledpads[5] master outpad_25um end
  gate ledpads[4] master outpad_25um end
  gate ledpads[3] master outpad_25um end
  gate ledpads[2] master outpad_25um end
  gate ledpads[1] master outpad_25um end
  gate ledpads[0] master outpad_25um end
  gate I201 master outpad_25um end
  gate I202 master outpad_25um end
  gate I203 master outpad_25um end
  gate I204 master outpad_25um end
  gate I205 master inpadff_25um end
  gate I207 master inpadff_25um end
  gate I208 master inpadff_25um end
  gate I209 master inpadff_25um end
  gate I165 master and3i2 end
  gate I166 master dff end
  gate I159 master and4i3 end
  gate I160 master dffe end
  gate I157 master and3i1 end
  gate I153 master or3i0 end
  gate I154 master and2i1 end
  gate I158 master and2i1 end
  gate I163 master Q_AND2I0 end
  gate I145 master or2i0 end
  gate I161 master or2i0 end
  gate Mst_WrData_Mux[31] master Q_MUX2X0 end
  gate Mst_WrData_Mux[30] master Q_MUX2X0 end
  gate Mst_WrData_Mux[29] master Q_MUX2X0 end
  gate Mst_WrData_Mux[28] master Q_MUX2X0 end
  gate Mst_WrData_Mux[27] master Q_MUX2X0 end
  gate Mst_WrData_Mux[26] master Q_MUX2X0 end
  gate Mst_WrData_Mux[25] master Q_MUX2X0 end
  gate Mst_WrData_Mux[24] master Q_MUX2X0 end
  gate Mst_WrData_Mux[23] master Q_MUX2X0 end
  gate Mst_WrData_Mux[22] master Q_MUX2X0 end
  gate Mst_WrData_Mux[21] master Q_MUX2X0 end
  gate Mst_WrData_Mux[20] master Q_MUX2X0 end
  gate Mst_WrData_Mux[19] master Q_MUX2X0 end
  gate Mst_WrData_Mux[18] master Q_MUX2X0 end
  gate Mst_WrData_Mux[17] master Q_MUX2X0 end
  gate Mst_WrData_Mux[16] master Q_MUX2X0 end
  gate Mst_WrData_Mux[15] master Q_MUX2X0 end
  gate Mst_WrData_Mux[14] master Q_MUX2X0 end
  gate Mst_WrData_Mux[13] master Q_MUX2X0 end
  gate Mst_WrData_Mux[12] master Q_MUX2X0 end
  gate Mst_WrData_Mux[11] master Q_MUX2X0 end
  gate Mst_WrData_Mux[10] master Q_MUX2X0 end
  gate Mst_WrData_Mux[9] master Q_MUX2X0 end
  gate Mst_WrData_Mux[8] master Q_MUX2X0 end
  gate Mst_WrData_Mux[7] master Q_MUX2X0 end
  gate Mst_WrData_Mux[6] master Q_MUX2X0 end
  gate Mst_WrData_Mux[5] master Q_MUX2X0 end
  gate Mst_WrData_Mux[4] master Q_MUX2X0 end
  gate Mst_WrData_Mux[3] master Q_MUX2X0 end
  gate Mst_WrData_Mux[2] master Q_MUX2X0 end
  gate Mst_WrData_Mux[1] master Q_MUX2X0 end
  gate Mst_WrData_Mux[0] master Q_MUX2X0 end
  gate mxled[7] master Q_MUX2X0 end
  gate mxled[6] master Q_MUX2X0 end
  gate mxled[5] master Q_MUX2X0 end
  gate mxled[4] master Q_MUX2X0 end
  gate mxled[3] master Q_MUX2X0 end
  gate mxled[2] master Q_MUX2X0 end
  gate mxled[1] master Q_MUX2X0 end
  gate mxled[0] master Q_MUX2X0 end
  gate I_124 master dffp end
  gate I149 master dffp end
  gate I218 master inv end
  gate I_129 master inv end
  gate ledinv[7] master inv end
  gate ledinv[6] master inv end
  gate ledinv[5] master inv end
  gate ledinv[4] master inv end
  gate ledinv[3] master inv end
  gate ledinv[2] master inv end
  gate ledinv[1] master inv end
  gate ledinv[0] master inv end
  gate I146 master inv end
  gate I_81 master inv end
  gate I212 master inv end
  gate I213 master inv end
  gate DMA.BRSTCNTR2.I4.QL5 master and5i4 end
  gate DMA.BRSTCNTR2.I4.QL4 master dnfxbit end
  gate DMA.BRSTCNTR2.I4.QL3 master dnfxbit end
  gate DMA.BRSTCNTR2.I4.QL2 master dnfxbit end
  gate DMA.BRSTCNTR2.I4.QL1 master dnfxbit end
  gate DMA.BRSTCNTR2.I5.QL4 master dnfxbit end
  gate DMA.BRSTCNTR2.I5.QL3 master dnfxbit end
  gate DMA.BRSTCNTR2.I5.QL2 master dnfxbit end
  gate DMA.BRSTCNTR2.I5.QL1 master dnfxbit end
  gate DMA.BRSTCNTR.I4.QL5 master and5i4 end
  gate DMA.BRSTCNTR.I4.QL4 master dnfxbit end
  gate DMA.BRSTCNTR.I4.QL3 master dnfxbit end
  gate DMA.BRSTCNTR.I4.QL2 master dnfxbit end
  gate DMA.BRSTCNTR.I4.QL1 master dnfxbit end
  gate DMA.BRSTCNTR.I5.QL4 master dnfxbit end
  gate DMA.BRSTCNTR.I5.QL3 master dnfxbit end
  gate DMA.BRSTCNTR.I5.QL2 master dnfxbit end
  gate DMA.BRSTCNTR.I5.QL1 master dnfxbit end
  gate DMA.WrCntReg.I_2.QL5 master and5i4 end
  gate DMA.WrCntReg.I_2.QL4 master dnfxbit end
  gate DMA.WrCntReg.I_2.QL3 master dnfxbit end
  gate DMA.WrCntReg.I_2.QL2 master dnfxbit end
  gate DMA.WrCntReg.I_2.QL1 master dnfxbit end
  gate DMA.WrCntReg.I_3.QL5 master and5i4 end
  gate DMA.WrCntReg.I_3.QL4 master dnfxbit end
  gate DMA.WrCntReg.I_3.QL3 master dnfxbit end
  gate DMA.WrCntReg.I_3.QL2 master dnfxbit end
  gate DMA.WrCntReg.I_3.QL1 master dnfxbit end
  gate DMA.WrCntReg.I4.QL5 master and5i4 end
  gate DMA.WrCntReg.I4.QL4 master dnfxbit end
  gate DMA.WrCntReg.I4.QL3 master dnfxbit end
  gate DMA.WrCntReg.I4.QL2 master dnfxbit end
  gate DMA.WrCntReg.I4.QL1 master dnfxbit end
  gate DMA.WrCntReg.I_1.QL4 master dnfxbit end
  gate DMA.WrCntReg.I_1.QL3 master dnfxbit end
  gate DMA.WrCntReg.I_1.QL2 master dnfxbit end
  gate DMA.WrCntReg.I_1.QL1 master dnfxbit end
  gate DMA.RdCntReg.I_2.QL5 master and5i4 end
  gate DMA.RdCntReg.I_2.QL4 master dnfxbit end
  gate DMA.RdCntReg.I_2.QL3 master dnfxbit end
  gate DMA.RdCntReg.I_2.QL2 master dnfxbit end
  gate DMA.RdCntReg.I_2.QL1 master dnfxbit end
  gate DMA.RdCntReg.I_3.QL5 master and5i4 end
  gate DMA.RdCntReg.I_3.QL4 master dnfxbit end
  gate DMA.RdCntReg.I_3.QL3 master dnfxbit end
  gate DMA.RdCntReg.I_3.QL2 master dnfxbit end
  gate DMA.RdCntReg.I_3.QL1 master dnfxbit end
  gate DMA.RdCntReg.I4.QL5 master and5i4 end
  gate DMA.RdCntReg.I4.QL4 master dnfxbit end
  gate DMA.RdCntReg.I4.QL3 master dnfxbit end
  gate DMA.RdCntReg.I4.QL2 master dnfxbit end
  gate DMA.RdCntReg.I4.QL1 master dnfxbit end
  gate DMA.RdCntReg.I_1.QL4 master dnfxbit end
  gate DMA.RdCntReg.I_1.QL3 master dnfxbit end
  gate DMA.RdCntReg.I_1.QL2 master dnfxbit end
  gate DMA.RdCntReg.I_1.QL1 master dnfxbit end
  gate DMA.RdAdrReg.un1_Q_1.CO6 master Q_INCSKIP2 pack end
  gate DMA.RdAdrReg.un1_Q_1.CO12 master Q_INCSKIP2 pack end
  gate DMA.RdAdrReg.un1_Q_1.CO18 master Q_INCSKIP2 pack end
  gate DMA.RdAdrReg.un1_Q_1.CO24 master Q_INCSKIP2 pack end
  gate DMA.RdAdrReg.un1_Q_1.CO27 master Q_INCSKIP pack end
  gate DMA.RdAdrReg.un1_Q_1.CO1 master Q_AND2 end
  gate DMA.RdAdrReg.un1_Q_1.CO2 master Q_AND2 end
  gate DMA.RdAdrReg.un1_Q_1.CO4 master Q_AND2 end
  gate DMA.RdAdrReg.un1_Q_1.CO5 master Q_AND2 end
  gate DMA.RdAdrReg.un1_Q_1.CO7 master Q_AND2 end
  gate DMA.RdAdrReg.un1_Q_1.CO8 master Q_AND2 end
  gate DMA.RdAdrReg.un1_Q_1.CO10 master Q_AND2 end
  gate DMA.RdAdrReg.un1_Q_1.CO11 master Q_AND2 end
  gate DMA.RdAdrReg.un1_Q_1.CO13 master Q_AND2 end
  gate DMA.RdAdrReg.un1_Q_1.CO14 master Q_AND2 end
  gate DMA.RdAdrReg.un1_Q_1.CO16 master Q_AND2 end
  gate DMA.RdAdrReg.un1_Q_1.CO17 master Q_AND2 end
  gate DMA.RdAdrReg.un1_Q_1.CO19 master Q_AND2 end
  gate DMA.RdAdrReg.un1_Q_1.CO20 master Q_AND2 end
  gate DMA.RdAdrReg.un1_Q_1.CO22 master Q_AND2 end
  gate DMA.RdAdrReg.un1_Q_1.CO23 master Q_AND2 end
  gate DMA.RdAdrReg.un1_Q_1.CO25 master Q_AND2 end
  gate DMA.RdAdrReg.un1_Q_1.CO26 master Q_AND2 end
  gate DMA.RdAdrReg.un1_Q_1.CO28 master Q_AND2 end
  gate DMA.RdAdrReg.un1_Q_1.SUM0 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM1 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM2 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM3 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM4 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM5 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM6 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM7 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM8 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM9 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM10 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM11 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM12 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM13 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM14 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM15 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM16 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM17 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM18 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM19 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM20 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM21 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM22 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM23 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM24 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM25 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM26 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM27 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM28 master Q_INCX end
  gate DMA.RdAdrReg.un1_Q_1.SUM29 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.CO6 master Q_INCSKIP2 pack end
  gate DMA.WrAdrReg.un1_Q_1.CO12 master Q_INCSKIP2 pack end
  gate DMA.WrAdrReg.un1_Q_1.CO18 master Q_INCSKIP2 pack end
  gate DMA.WrAdrReg.un1_Q_1.CO24 master Q_INCSKIP2 pack end
  gate DMA.WrAdrReg.un1_Q_1.CO27 master Q_INCSKIP pack end
  gate DMA.WrAdrReg.un1_Q_1.CO1 master Q_AND2 end
  gate DMA.WrAdrReg.un1_Q_1.CO2 master Q_AND2 end
  gate DMA.WrAdrReg.un1_Q_1.CO4 master Q_AND2 end
  gate DMA.WrAdrReg.un1_Q_1.CO5 master Q_AND2 end
  gate DMA.WrAdrReg.un1_Q_1.CO7 master Q_AND2 end
  gate DMA.WrAdrReg.un1_Q_1.CO8 master Q_AND2 end
  gate DMA.WrAdrReg.un1_Q_1.CO10 master Q_AND2 end
  gate DMA.WrAdrReg.un1_Q_1.CO11 master Q_AND2 end
  gate DMA.WrAdrReg.un1_Q_1.CO13 master Q_AND2 end
  gate DMA.WrAdrReg.un1_Q_1.CO14 master Q_AND2 end
  gate DMA.WrAdrReg.un1_Q_1.CO16 master Q_AND2 end
  gate DMA.WrAdrReg.un1_Q_1.CO17 master Q_AND2 end
  gate DMA.WrAdrReg.un1_Q_1.CO19 master Q_AND2 end
  gate DMA.WrAdrReg.un1_Q_1.CO20 master Q_AND2 end
  gate DMA.WrAdrReg.un1_Q_1.CO22 master Q_AND2 end
  gate DMA.WrAdrReg.un1_Q_1.CO23 master Q_AND2 end
  gate DMA.WrAdrReg.un1_Q_1.CO25 master Q_AND2 end
  gate DMA.WrAdrReg.un1_Q_1.CO26 master Q_AND2 end
  gate DMA.WrAdrReg.un1_Q_1.CO28 master Q_AND2 end
  gate DMA.WrAdrReg.un1_Q_1.SUM0 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM1 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM2 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM3 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM4 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM5 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM6 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM7 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM8 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM9 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM10 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM11 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM12 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM13 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM14 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM15 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM16 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM17 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM18 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM19 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM20 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM21 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM22 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM23 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM24 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM25 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM26 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM27 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM28 master Q_INCX end
  gate DMA.WrAdrReg.un1_Q_1.SUM29 master Q_INCX end