ct_target.tf

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

		$display("\t... Passed");
		PERR_Detected = 0;
		end
	else $display("\t... *** Failed ***");

master_2.data_array[0] = 32'h001011e3;
master_2.data_array[1] = 32'h0280016A;
master_2.data_array[2] = 32'hFF000001;
master_2.data_array[3] = 32'h00004000;
master_2.data_array[4] = 32'h22000000;

repeat (5) @(posedge CLK);
$display ("Resetting the Device for Memory Read/Write Test, %0d", $time);
master_2.target_access_pf(32'h0,32'h0,CONFIG_WRITE,8'hFF,1'b0,1'b0,5,2,3,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... Passed");
	Master_Abort_Detected = 1;
	end
else $display("\t...*** Failed ***");

repeat (5) @(posedge CLK);
$display ("Memory Write/Memory Read Test, %0d", $time);
for (i = 0; i < 256; i = i + 1) begin
	master_2.data_array[i] = 32'hFFFFFFFF;
	master_2.be_array[i] = 4'hF;
	end
master_2.target_access_pf(32'h22000000,32'h0,MEM_WRITE,8'hFF,1'b0,1'b0,256,0,0,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... Passed");
	Master_Abort_Detected = 1;
	end
else $display("\t...*** Failed ***");

master_2.data_array[64] = 32'hFFFFFFFF;
master_2.data_array[65] = 32'hFFFFFFFC;
master_2.data_array[66] = 32'hFFFFFFFC;
master_2.data_array[67] = 32'hFFFFFF00;
master_2.data_array[68] = 32'h00000000;
master_2.data_array[69] = 32'h00000007;
master_2.data_array[70] = 32'h007701FF;
master_2.be_array[68] = 4'b1000;  // Random numbers in lower 24 bits of the performance counter

repeat (5) @(posedge CLK);
master_2.target_access_pf(32'h22000000,32'h0,MEM_READ,8'hFF,1'b0,1'b0,256,0,0,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... Passed");
	Master_Abort_Detected = 1;
	end
else $display("\t...*** Failed ***");

repeat (5) @(posedge CLK);
$display ("Memory Write & Invalidate / Memory Read Line Test, %0d", $time);
for (i = 0; i < 6; i = i + 1) begin
	master_2.data_array[i] = 32'h00000000;
	if (i == 0) master_2.be_array[i] = 4'b0011;
	else case(master_2.be_array[i-1])
		4'b0011 : master_2.be_array[i] = 4'b0110;
		4'b0110 : master_2.be_array[i] = 4'b1100;
		4'b1100 : master_2.be_array[i] = 4'b1001;
		4'b1001 : master_2.be_array[i] = 4'b0011;
		endcase
	end
master_2.target_access_pf(32'h22000100,32'h0,MEM_WR_INVALID,8'hFF,1'b0,1'b0,6,2,3,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... Passed");
	Master_Abort_Detected = 1;
	end
else $display("\t...*** Failed ***");

master_2.data_array[0] = 32'hFFFF0000;
master_2.data_array[1] = 32'hFFFFFFFC;
master_2.data_array[2] = 32'hFFFFFFFC;
master_2.data_array[3] = 32'h00FFFF00;	// WrEn bit goes low because WrCnt was reset to 0000
master_2.data_array[4] = 32'h00000000;
master_2.data_array[5] = 32'h00000007;
for (i = 0; i < 6; i = i + 1) begin
	master_2.be_array[i] = 4'hF;
	end
master_2.be_array[4] = 4'b1000;  // Random numbers in lower 24 bits of the performance counter

repeat (5) @(posedge CLK);
master_2.target_access_pf(32'h22000100,32'h0,MEM_READ_LINE,8'hFF,1'b0,1'b0,6,2,3,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... Passed");
	Master_Abort_Detected = 1;
	end
else $display("\t...*** Failed ***");


repeat (5) @(posedge CLK);
$display ("Memory Write & Invalidate / Memory Read Multiple Test, %0d", $time);
for (i = 0; i < 6; i = i + 1) begin
	master_2.data_array[i] = 32'hAAAAAAAA;
	if (i == 0) master_2.be_array[i] = 4'b1100;
	else case(master_2.be_array[i-1])
		4'b0011 : master_2.be_array[i] = 4'b0110;
		4'b0110 : master_2.be_array[i] = 4'b1100;
		4'b1100 : master_2.be_array[i] = 4'b1001;
		4'b1001 : master_2.be_array[i] = 4'b0011;
		endcase
	end
master_2.target_access_pf(32'h22000100,32'h0,MEM_WR_INVALID,8'hFF,1'b0,1'b0,6,1,0,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... Passed");
	Master_Abort_Detected = 1;
	end
else $display("\t...*** Failed ***");

master_2.data_array[0] = 32'hAAAA0000;
master_2.data_array[1] = 32'hFFFFFFFC;
master_2.data_array[2] = 32'hFFFFFFFC;
master_2.data_array[3] = 32'h00AAAA00;	// WrEn bit goes low because WrCnt was reset to 0000
master_2.data_array[4] = 32'h00000000;
master_2.data_array[5] = 32'h00000002;
for (i = 0; i < 6; i = i + 1) begin
	master_2.be_array[i] = 4'hF;
	end
master_2.be_array[4] = 4'b1000;  // Random numbers in lower 24 bits of the performance counter

repeat (5) @(posedge CLK);
master_2.target_access_pf(32'h22000100,32'h0,MEM_READ_MULT,8'hFF,1'b0,1'b0,6,1,0,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... Passed");
	Master_Abort_Detected = 1;
	end
else $display("\t...*** Failed ***");

master_2.data_array[0] = 32'h001011e3;
master_2.data_array[1] = 32'h02000162;
master_2.data_array[2] = 32'h02000001;
master_2.data_array[3] = 32'h00001000;
master_2.data_array[4] = 32'h22000000;
for (i = 0; i < 6; i = i + 1) begin
	master_2.be_array[i] = 4'hF;
	end

repeat (5) @(posedge CLK);
$display ("Resetting the Device for Memory Read/Write Test");
master_2.target_access_pf(32'h0,32'h0,CONFIG_WRITE,8'hFF,1'b0,1'b0,5,2,3,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... Passed");
	Master_Abort_Detected = 1;
	end
else $display("\t...*** Failed ***");

repeat (5) @(posedge CLK);
$display ("Memory Write/Memory Read Test (Reserved Mode 01), %0d", $time);
for (i = 0; i < 6; i = i + 1) begin
	master_2.data_array[i] = 32'hFFFFFFFF;
	master_2.be_array[i] = 4'hF;
	end
master_2.target_access_pf(32'h22000101,32'h0,MEM_WRITE,8'hFF,1'b0,1'b0,6,2,3,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... Passed");
	Master_Abort_Detected = 1;
	end
else $display("\t...*** Failed ***");

master_2.data_array[0] = 32'hFFFFFFFF;
master_2.data_array[1] = 32'hFFFFFFFC;
master_2.data_array[2] = 32'hFFFFFFFC;
master_2.data_array[3] = 32'hFFFFFF00;
master_2.data_array[4] = 32'h00000000;
master_2.data_array[5] = 32'h00000007;
master_2.be_array[4] = 4'b1000;  // Random numbers in lower 24 bits of the performance counter

repeat (5) @(posedge CLK);
master_2.target_access_pf(32'h22000101,32'h0,MEM_READ,8'hFF,1'b0,1'b0,6,2,3,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... Passed");
	Master_Abort_Detected = 1;
	end
else $display("\t...*** Failed ***");

repeat (5) @(posedge CLK);
$display ("Memory Write & Invalidate / Memory Read Line Test (Reserved Mode 10), %0d", $time);
for (i = 0; i < 6; i = i + 1) begin
	master_2.data_array[i] = 32'h00000000;
	if (i == 0) master_2.be_array[i] = 4'b0011;
	else case(master_2.be_array[i-1])
		4'b0011 : master_2.be_array[i] = 4'b0110;
		4'b0110 : master_2.be_array[i] = 4'b1100;
		4'b1100 : master_2.be_array[i] = 4'b1001;
		4'b1001 : master_2.be_array[i] = 4'b0011;
		endcase
	end
master_2.target_access_pf(32'h22000102,32'h0,MEM_WR_INVALID,8'hFF,1'b0,1'b0,6,2,3,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... Passed");
	Master_Abort_Detected = 1;
	end
else $display("\t...*** Failed ***");

master_2.data_array[0] = 32'hFFFF0000;
master_2.data_array[1] = 32'hFFFFFFFC;
master_2.data_array[2] = 32'hFFFFFFFC;
master_2.data_array[3] = 32'h00FFFF00;	// WrEn bit goes low because WrCnt was reset to 0000
master_2.data_array[4] = 32'h00000000;
master_2.data_array[5] = 32'h00000007;
for (i = 0; i < 6; i = i + 1) begin
	master_2.be_array[i] = 4'hF;
	end
master_2.be_array[4] = 4'b1000;  // Random numbers in lower 24 bits of the performance counter

repeat (5) @(posedge CLK);
master_2.target_access_pf(32'h22000102,32'h0,MEM_READ_LINE,8'hFF,1'b0,1'b0,6,2,3,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... Passed");
	Master_Abort_Detected = 1;
	end
else $display("\t...*** Failed ***");


repeat (5) @(posedge CLK);
$display ("Memory Write & Invalidate / Memory Read Multiple Test (Reserved Mode 11), %0d", $time);
for (i = 0; i < 6; i = i + 1) begin
	master_2.data_array[i] = 32'hAAAAAAAA;
	if (i == 0) master_2.be_array[i] = 4'b1100;
	else case(master_2.be_array[i-1])
		4'b0011 : master_2.be_array[i] = 4'b0110;
		4'b0110 : master_2.be_array[i] = 4'b1100;
		4'b1100 : master_2.be_array[i] = 4'b1001;
		4'b1001 : master_2.be_array[i] = 4'b0011;
		endcase
	end
master_2.target_access_pf(32'h22000103,32'h0,MEM_WR_INVALID,8'hFF,1'b0,1'b0,6,1,0,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... Passed");
	Master_Abort_Detected = 1;
	end
else $display("\t...*** Failed ***");

master_2.data_array[0] = 32'hAAAA0000;
master_2.data_array[1] = 32'hFFFFFFFC;
master_2.data_array[2] = 32'hFFFFFFFC;
master_2.data_array[3] = 32'h00AAAA00;	// WrEn bit goes low because WrCnt was reset to 0000
master_2.data_array[4] = 32'h00000000;
master_2.data_array[5] = 32'h00000002;
for (i = 0; i < 6; i = i + 1) begin
	master_2.be_array[i] = 4'hF;
	end
master_2.be_array[4] = 4'b1000;  // Random numbers in lower 24 bits of the performance counter

repeat (5) @(posedge CLK);
master_2.target_access_pf(32'h22000103,32'h0,MEM_READ_MULT,8'hFF,1'b0,1'b0,6,1,0,1'b0, pass, 1'b0); 
if (~Master_Abort_Detected) begin
	$display("\t... Passed");
	Master_Abort_Detected = 1;
	end
else $display("\t...*** Failed ***");

$display ("Configure Target for normal waits, 0 retrys\n");
	repeat (5) @(posedge CLK);
	master_2.target_access_pf(32'h22000118,32'h00000000,MEM_WRITE,8'hFF,1'b0,1'b0,1,2,3,1'b0, pass, 1'b0); 


repeat (5) @(posedge CLK);
$display ("Burst Accross the Device Boundary Test, %0d", $time);
for (i = 0; i < 6; i = i + 1) begin
	master_2.data_array[i] = 32'hFFFFFFFF;
	master_2.be_array[i] = 4'hF;
	end
Disconnect_Detected = 0;
master_2.target_access_pf(32'h220003F0,32'h0,MEM_WRITE,8'hFF,1'b0,1'b0,6,2,3,1'b0, pass, 1'b0); 
if (Disconnect_Detected) begin
	$display("\t... Passed");
	Disconnect_Detected = 0;
	end
else $display("\t...*** Failed ***");

repeat (5) @(posedge CLK);
$display("Memory Read Address Parity Error Test: Target should assert SERRN, %0d", $time);
master_2.generate_bad_parity(1);
master_2.target_access(32'h22000100,64'h0,MEM_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0); 
if (SERR_Detected) begin
	$display("\t... Passed");
	SERR_Detected = 0;
	end
else $display("\t... *** Failed ***");

repeat (5) @(posedge CLK);
$display("Memory Read Line Address Parity Error Test: Target should assert SERRN, %0d", $time);
master_2.generate_bad_parity(1);
master_2.target_access(32'h22000100,64'h0,MEM_READ_LINE,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0); 
if (SERR_Detected) begin
	$display("\t... Passed");
	SERR_Detected = 0;
	end
else $display("\t... *** Failed ***");

repeat (5) @(posedge CLK);
$display("Memory Read Multiple Address Parity Error Test: Target should assert SERRN, %0d", $time);
master_2.generate_bad_parity(1);
master_2.target_access(32'h22000100,64'h0,MEM_READ_MULT,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0); 
if (SERR_Detected) begin
	$display("\t... Passed");
	SERR_Detected = 0;
	end
else $display("\t... *** Failed ***");

repeat (5) @(posedge CLK);
$display("Memory Write Address Parity Error Test: Target should assert SERRN, %0d", $time);
master_2.generate_bad_parity(1);
master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0); 
if (SERR_Detected) begin
	$display("\t... Passed");
	SERR_Detected = 0;
	end
else $display("\t... *** Failed ***");

repeat (5) @(posedge CLK);
$display("Memory Write and Invalidate Address Parity Error Test: Target should assert SERRN, %0d", $time);
master_2.generate_bad_parity(1);
master_2.target_access(32'h22000100,64'h0,MEM_WR_INVALID,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0); 
if (SERR_Detected) begin
	$display("\t... Passed");
	SERR_Detected = 0;
	end
else $display("\t... *** Failed ***");

repeat (5) @(posedge CLK);
$display("Memory Write Data (Phase 1) Parity Error Test: Target should assert PERRN, %0d", $time);
PERR_Detected = 0;
master_2.generate_bad_parity(3);
master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,7'h03,4'h1,4'h1,1'b0); 
if (PERR_Detected) begin
	$display("\t... Passed");
	PERR_Detected = 0;
	end
else $display("\t... *** Failed ***");

$display("Memory Write Data (Phase 2) Parity Error Test: Target should assert PERRN, %0d", $time);
	repeat (5) @(posedge CLK);
	master_2.generate_bad_parity(5);
	master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,7'h03,4'h1,4'h1,1'b0); 
	if (PERR_Detected) begin
		$display("\t... Passed");
		PERR_Detected = 0;
		end
	else $display("\t... *** Failed ***");

$display("Memory Write and Invalidate Data (Phase 1) Parity Error Test: Target should assert PERRN, %0d", $time);
	repeat (5) @(posedge CLK);
	PERR_Detected = 0;
	master_2.generate_bad_parity(3);
	master_2.target_access(32'h22000100,64'h0,MEM_WR_INVALID,8'hFF,1'b0,1'b0,7'h03,4'h1,4'h1,1'b0); 
	if (PERR_Detected) begin
		$display("\t... Passed");
		PERR_Detected = 0;
		end
	else $display("\t... *** Failed ***");

$display("Memory Write and Invalidate Data (Phase 2) Parity Error Test: Target should assert PERRN, %0d", $time);
	repeat (5) @(posedge CLK);
	master_2.generate_bad_parity(5);
	master_2.target_access(32'h22000100,64'h0,MEM_WR_INVALID,8'hFF,1'b0,1'b0,7'h03,4'h1,4'h1,1'b0); 
	if (PERR_Detected) begin
		$display("\t... Passed");
		PERR_Detected = 0;
		end
	else $display("\t... *** Failed ***");