cfgtaddr_cardbus.v

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

//------------------------------------------------------------------------------
//
// File : cfgtaddr_cardbus.v
// Last Modification: 10/26/2003
//
// Created In SpDE Version: SpDE 9.5.1
// Author :	QuickLogic Corporation
// Copyright (C) 2003, Licensed customers of QuickLogic may copy and modify
// this file for use in designing with QuickLogic devices only.
//	
// Description : This is a block in the QuickPCI programmable logic region.
//	It contains 3 sections:
//		config space
//		target address register/counter
//		command decode
//
//	Main differences from regular QL5632 (and higher) configuration space
//	1.  PCI Command Register:  "Memory Space enable", "Parity Error Response", 
//		and "SERR# enable" bits are always implemented (ie not fixed).
//	2.	PCI Status Register:  "Signaled System Error", and "Detected Parity Error"
//		bits are always implemented (ie not fixed).
//	3.  QuickPCI already ignores "Interrupt Acknowledge" and "Dual Access Cycle" commands.
//	4.  Added CardBus_CIS:  CIS is set to be in memory space, starting at BAR5 offset 0.
//	 
// Hierarchy:
//	This file represents the configuration space in the top-level design.
//
// History:	
//	Date	        Author					Version
//	10/26/03		David Shih				1.0
//		- Initial release. Modifed from cfgtaddr_5632_280.v in 5632 ref design.
//
//------------------------------------------------------------------------------


`timescale 1ns/1ns

module cfgtaddr_cardbus( // config space ports
                      CBE, Cfg_Write, PCI_clock, CacheLineSizeReg, CmdReg, WrData, MstPERR_Det, PERR_Det,
                      TTO_Det, LatTimerReg, PCI_reset, SERR_Sig, Tabort_Det, CfgData, MstSC,

                 // target address register/counter ports
                      LoadAddr, IncrAddr, Addr_Hit, Usr_Stop, UsrAddr,
					  BAR0_Hit, BAR5_Hit, // DS added

                 // command decode ports
                      Usr_RdCmd, Usr_WrCmd
               );


parameter BAR0_size = 10;                 // Sets the size of the requested memory space.
                                          //   Default value is 10, corresponding to 1KB.
                                          //   (# of bits to tie off in the BAR)

parameter BAR5_size = 10;	// DS for CIS
               
// config space ports               
input [3:0] CBE;
input [31:0] WrData;
input Cfg_Write, PCI_clock, MstPERR_Det, PERR_Det, TTO_Det, PCI_reset, SERR_Sig, Tabort_Det, MstSC;
output [31:0] CfgData  /* synthesis syn_preserve=1 */;
output [15:0] CmdReg;
output [7:0] LatTimerReg;
reg [31:0] CfgData;
wire [15:0] CmdReg;
wire [7:0] LatTimerReg;

// target address reg/counter ports
input LoadAddr;
input IncrAddr;
output Addr_Hit;
output	BAR0_Hit;	// DS added
output	BAR5_Hit;	// DS added
output Usr_Stop; 
output [BAR0_size-1:0] UsrAddr;	//the width of this port can be changed if the size
						//  of the memory space is changed (base addr reg) 
reg [BAR0_size-1:0] UsrAddr;

// command decode ports
output Usr_RdCmd, Usr_WrCmd;

output [7:2] CacheLineSizeReg;
wire [7:2] CacheLineSizeReg;

// ************************
// ***   config space   ***
// ************************

// *** Full 32-bit wide PCI registers    offset
wire [31:0] Dev_Vend;                // 00h
wire [31:0] Stat_Cmd;                // 04h
wire [31:0] Class_RevID;             // 08h
wire [31:0] BIST_Hdr_Lat_Cache;      // 0Ch
wire [31:0] BAR0;                    // 10h
wire [31:0] BAR5;                    // 24h  DS for CIS
wire [31:0] SubsysID_SubsysVendID;   // 2Ch
wire [31:0] Lat_Gnt_IntPin_IntLine;  // 3Ch


// *** declarations for hard-wired and writable parameters

// *********** beginning of user-modifiable parameters ************

// PCI registers                          offset into config space
wire [15:0] DeviceID = 16'h001E;          // 00h  0x1e is the code for QL5632-33PT280
wire [15:0] VendorID = 16'h11E3;          // 00h
wire [23:0] ClassCode = 24'hFF0000;       // 08h Class Code Not Defined (FF)
wire [7:0] RevisionID = 8'h00;            // 08h
wire [31:0] Cardbus_CIS = 32'h00000006;   // 28h [3:0] of 1 to 6 means CIS is in BAR1-6
wire [15:0] SubsysID = 16'h0002;          // 2Ch  0x2 is the code for the PCI32RDK-280 board
wire [15:0] SubsysVendID = 16'h11E3;      // 2Ch
wire [31:0] Expansion_ROM = 32'h00000000; // 30h
wire [7:0] MaxLat = 8'h10;                // 3Ch 8 clocks * MaxLat = Maximum Wait between Grants (128)
wire [7:0] MinGnt = 8'h08;                // 3Ch 8 clocks * MinGnt = Minimum Burst Clocks Required (64)
wire [7:0] IntPin = 8'h00;                // 3Ch No Interrupts Used.  Set to 8'h01 for INTA support.

// *********** end of user-modifiable parameters ************


// Command register (offset 04h) ................ bit
wire IOEnable                    = 0;    //   0   - always 0
reg  MemEnable                      ;    //   1   - FF - memory device, off by default until enabled
reg  BusMasterEnable                ;    //   2   - initiator enable
reg  SpecialCycleEnable             ;    //   3   - special cycles
reg  MemWrAndInvalidateEnable       ;    //   4   - mem write & invalidate
wire VGAPaletteSnoopEnable       = 0;    //   5   - no palette snoop capability
reg  ParityErrorEnable              ;    //   6   - parity error enable
wire WaitCycleControl            = 0;    //   7   - addr/data stepping never done
reg  SERREnable                     ;    //   8   - SERRn enable 
wire FastBack2BackEnable         = 0;    //   9   - Fast back to back never done
                                         // 15-10 - reserved


// Status register (offset 04h) ...........  bit
//                                           0-3  - reserved
wire NewCapabilities		   = 0;      //   4   - no new capabilities
wire Capable66MHz              = 0;      //   5   - not 66MHz capable
//                                       //   6   - reserved
wire FastBack2BackCapable      = 1;      //   7   - target is fast back-to-back capable
reg  DataParErrorDetected         ;      //   8   - 
wire [1:0] DevselTiming        = 2'b01;  // 10-9  - medium speed devsel assertion
// comment wire declaration and uncomment reg declaration for designs
//     that are capable of generating target aborts
// reg  SignaledTargetAbort          ;      //  11   - signaled target abort as target
wire SignaledTargetAbort       = 0;      //  11   - target abort never generated
reg  ReceivedTargetAbort          ;      //  12   - 
reg  ReceivedMasterAbort          ;      //  13   - 
reg  SignaledSystemError          ;      //  14   - 
reg  ParErrorDetected             ;      //  15   - 


// registers at offset 0Ch
wire [7:0] HeaderType = 8'h00;
wire [7:0] BIST = 8'h00;
reg [7:0] LatTimer;
reg [7:2] CacheLineSize;		// needed for implementing Memory Write and Invalidate, must be at least 4

// base address registers (BAR's)
reg [31:BAR0_size] BAR0_reg;
wire [BAR0_size-1:0] BAR0_lower = 0;
// DS for CIS
reg [31:BAR5_size] BAR5_reg;
wire [BAR5_size-1:0] BAR5_lower = 0;
wire	BAR0_Hit_int;
wire	BAR5_Hit_int;
reg 	CIS_Hit;

// registers at offset 3Ch
// Comment wire declaration and uncomment reg declaration for Interrupt Support
// reg [7:0] IntLine;
wire [7:0] IntLine = 8'h00;

// Usr_Stop Signal is used to signal that the next transfer must be cancelled.
reg Usr_Stop;

// address for config address decodes
reg [3:0] cfgadr;

// *** assignments that construct the 32-bit wide PCI config registers

// offset 00h
assign #1 Dev_Vend = {DeviceID[15:0], VendorID[15:0]};

// offset 04h
assign #1 Stat_Cmd = {   //status register
                         ParErrorDetected,
                         SignaledSystemError,
                         ReceivedMasterAbort,
                         ReceivedTargetAbort,
                         SignaledTargetAbort,
                         DevselTiming[1:0],
                         DataParErrorDetected,
                         FastBack2BackCapable,
                         1'b0, //bit 6 is reserved
                         Capable66MHz,
						 NewCapabilities,
                         4'b0, //bits 3:0 reserved
                         //command register:
                         6'b0, //bits 15:10 reserved
                         FastBack2BackEnable,
                         SERREnable,
                         WaitCycleControl,
                         ParityErrorEnable,
                         VGAPaletteSnoopEnable,
                         MemWrAndInvalidateEnable,
                         SpecialCycleEnable,
                         BusMasterEnable,
                         MemEnable,
                         IOEnable
                     };

// offset 08h
assign #1 Class_RevID = {ClassCode[23:0], RevisionID[7:0]};

// offset 0Ch
assign #1 BIST_Hdr_Lat_Cache = {BIST[7:0], HeaderType[7:0], LatTimer[7:0], CacheLineSize[7:2], 2'b00};

// offset 10h
assign #1 BAR0 = {BAR0_reg,BAR0_lower};

// DS for CIS, offset 24h
assign #1 BAR5 = {BAR5_reg,BAR5_lower};

// offset 2Ch
assign #1 SubsysID_SubsysVendID = {SubsysID,SubsysVendID};

// offset 3Ch