updcnt6.v

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

`timescale 1ns/1ns
`define updcnt6
/************************************************************************
** File : updcnt6.v
** Design Date: June 9, 1998
** Creation Date: Thu Sep 21 17:00:30 2000
** Created By SpDE Version: SpDE 8.2 
** Author: Brian Faith, QuickLogic Corporation,
** Copyright (C) 1998, Customers of QuickLogic may copy and modify this
** file for use in designing QuickLogic devices only.
** Description: This is the counter for generating the read
** and write addresses in the FIFOs.
************************************************************************/
module updcnt6 (up, down, clk, q, rst);

// inputs: up,down,clk,rst
// outputs: =q[5:0]=

input up, down, clk, rst;
output [5:0] q;
reg [5:0] q;

always @(posedge clk or posedge rst) begin
   if (rst)
      q <= #1 0;
   else
      case ({up, down})
         2'b00 : q <= #1 q;
         2'b01 : q <= #1 q - 1;
         2'b10 : q <= #1 q + 1;
         2'b11 : q <= #1 q;
      endcase
end
endmodule