rgec5_1r.v

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

//------------------------------------------------------------------------------
//
// File : rgec5_1r.v
// Last Modification: 06/26/2001
//
// Created In SpDE Version: SpDE 8.22
// Author :	Richard Yuan, QuickLogic Corporation
// Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
// this file for use in designing with QuickLogic devices only.
//	
// Description :
//	5-bit register with a reset value of 0.
//	Q_int is the binary decode of the grey register value, for simulation only.
//
// Hierarchy:
//	This file represents the rgec5_1r block in f32a32.sch.
//
// History:	
//	Date	        Author					Version
//  06/26/01		Richard Yuan			1.0
//		- Header added to conform to coding standard.
//
//------------------------------------------------------------------------------


module rgec5_1r ( CLK, CLR, EN, D, Q );
input CLK, CLR, EN;
input  [4:0] D;
output [4:0] Q;
reg    [4:0] Q;
integer Q_int;

always @(posedge CLR or posedge CLK)
begin
    if (CLR)    // reset grey 0 = bin 0, inc to 1 on init
        Q <= 0;
    else if (EN)   // load
        Q <= D;
end

always @(Q) begin
    case (Q)
        5'b00000: Q_int <=  0;
        5'b00001: Q_int <=  1;
        5'b00011: Q_int <=  2;
        5'b00010: Q_int <=  3;
        5'b00110: Q_int <=  4;
        5'b00111: Q_int <=  5;
        5'b00101: Q_int <=  6;
        5'b00100: Q_int <=  7;
        5'b01100: Q_int <=  8;
        5'b01101: Q_int <=  9;
        5'b01111: Q_int <=  10;
        5'b01110: Q_int <=  11;
        5'b01010: Q_int <=  12;
        5'b01011: Q_int <=  13;
        5'b01001: Q_int <=  14;
        5'b01000: Q_int <=  15;
        5'b11000: Q_int <=  16;
        5'b11001: Q_int <=  17;
        5'b11011: Q_int <=  18;
        5'b11010: Q_int <=  19;
        5'b11110: Q_int <=  20;
        5'b11111: Q_int <=  21;
        5'b11101: Q_int <=  22;
        5'b11100: Q_int <=  23;
        5'b10100: Q_int <=  24;
        5'b10101: Q_int <=  25;
        5'b10111: Q_int <=  26;
        5'b10110: Q_int <=  27;
        5'b10010: Q_int <=  28;
        5'b10011: Q_int <=  29;
        5'b10001: Q_int <=  30;
        5'b10000: Q_int <=  31;
        default: Q_int <= 0;
    endcase
end

endmodule