fifocont.v

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

//------------------------------------------------------------------------------
//
// File : fifocont.v
// Last Modification: 06/26/2001
//
// Created In SpDE Version: SpDE 8.22
// Author :	Richard Yuan, QuickLogic Corporation
// Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
// this file for use in designing with QuickLogic devices only.
//	
// Description :
//	This is the controller of the external IDT FIFO chip.
//
// Hierarchy:
//	This file represents the fifocont block in pci5(3/4)32_280.sch.
//
// History:	
//	Date	        Author					Version
//  06/26/01		Richard Yuan			1.0
//		- Header reorganized to conform to coding standard.
//
//------------------------------------------------------------------------------


module fifocont (clk, clr, we, we_int, re, re_dly, fpga_oe, idt_fifo_oe_n,
					idt_fifo_full, idt_fifo_af_n, idt_fifo_empty, idt_fifo_ae_n,
					rbuff_empty, rbuff_ae, wbuff_full, wbuff_af, ldn);

	input clk, clr, idt_fifo_full, idt_fifo_af_n, idt_fifo_empty, idt_fifo_ae_n;
	input rbuff_empty, rbuff_ae, wbuff_full, wbuff_af;
	output we, re, we_int, re_dly, fpga_oe, idt_fifo_oe_n, ldn;

	reg [5:0] fstate /* synthesis syn_preserve = 1 */;
	reg init, ldn, we_dly, re_dly;
	wire re_int;

	parameter fifo_read  	= 6'b110010;
	parameter prep_read  	= 6'b100000;
	parameter fifo_write 	= 6'b001101;
	parameter prep_write	= 6'b000100;
	parameter idle			= 6'b000000;

always @(posedge clk or posedge clr) begin
	if (clr) fstate <= idle;
	else
			case (fstate)

				idle:			if (~idt_fifo_full && ~rbuff_empty) fstate <= prep_write;
								else if (~idt_fifo_empty && ~wbuff_full) fstate <= prep_read;
								else fstate <= idle;

				prep_write:		if (~idt_fifo_full) fstate <= fifo_write;
								else fstate <= idle;

				fifo_write: if (~idt_fifo_af_n || rbuff_ae) fstate <= idle;
								else fstate <= fifo_write;

				prep_read:	if (~idt_fifo_empty && ~wbuff_full) fstate <= fifo_read;
								else fstate <= idle;
	
				fifo_read:	if (~idt_fifo_ae_n || wbuff_af) fstate <= idle;
								else fstate <= fifo_read;
 
				default:		fstate <= 6'bxxxxxx;  // for a faster implementation

		endcase
	end

// optimized state assignment allows direct state bit mapping to outputs
assign we = fstate[0];
assign we_int = fstate[3];
assign re = fstate[1];
assign re_int = fstate[4];
assign fpga_oe = fstate[2];
assign idt_fifo_oe_n = fstate[2];

// make sure ldn is active for the first two we pulses
always @(posedge clk or posedge clr)
	if (clr) init <= 0;
	else if (we_dly && we_int) init <= 1;

always @(posedge clk or posedge clr)
	if (clr) we_dly <= 0;
	else if (we_int) we_dly <= 1;

always @(posedge clk or posedge clr)
	if (clr) ldn <= 0;
	else if (init) ldn <= 1;

always @(posedge clk or posedge clr)
	if (clr) re_dly <= 0;
	else if (~wbuff_full) re_dly <= re_int;

endmodule