📄 cmd_monitor.tf
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//------------------------------------------------------------------------------
// File : cmd_moniter.tf
// Last Modification: November 12th 2002
//
// Created In SpDE Version: SpDE 9.4 alpha (Build 1)
// Author: Nannapaneni P Rao, QuickLogic Corporation
// Copyright (C) 2002, Licensed Customers of QuickLogic may copy and
// modify this file for use in designing QuickLogic devices only.
//
// Description :
// This file contains the command Moniter program, for displaying
// various transactions on the pci bus during simulation
//
//
// Hierarchy:
// Library Modules used : None
// Other Modules used : none
//
// History:
// Date Author Version
// Nov 12th '02 : Nannapaneni P Rao Version 0.0
//
// Status:
// This design in the current version was simulated as it is.
// and it is working
//
//------------------------------------------------------------------------------
module cmd_monitor (ad,cben,clk,devseln,framen,idsel,irdyn,par,perrn,rstn,
serrn,stopn,trdyn,test_type,cmd_mon);
input [63:0] ad;
input [7:0] cben;
input clk,devseln,framen,idsel,irdyn,par;
input perrn,rstn,serrn,stopn,trdyn;
input [7:0] test_type;
output [7:0] cmd_mon;
reg [7:0] cmd_mon;
// declare PCI_CMD parameters
parameter idle = 8'h00,
IA = 8'h01,
I_A = 8'h02,
SC = 8'h03,
S_C = 8'h04,
IO_R = 8'h05,
I_O_R = 8'h06,
IO_W = 8'h07,
I_O_W = 8'h08,
Res4 = 8'h09,
Res_4 = 8'h0a,
Res5 = 8'h0b,
Res_5 = 8'h0c,
MR = 8'h0d,
M_R = 8'h0e,
MW = 8'h0f,
M_W = 8'h10,
Res8 = 8'h11,
Res_8 = 8'h12,
Res9 = 8'h13,
Res_9 = 8'h14,
CR = 8'h15,
C_R = 8'h16,
CW = 8'h17,
C_W = 8'h18,
Mem_R_M = 8'h19,
MRM = 8'h1a,
D_A_C = 8'h1b,
DAC = 8'h1c,
M_R_L = 8'h1d,
MRL = 8'h1e,
M_W_I = 8'h1f,
MWI = 8'h20;
// Configuration Space Parameters
parameter None = 8'h30,
Dev_Vend = 8'h31,
Stat_Cmd = 8'h32,
Clas_Rev = 8'h33,
BHLC = 8'h34,
BAR0 = 8'h35,
BAR1 = 8'h36,
BAR2 = 8'h37,
BAR3 = 8'h38,
BAR4 = 8'h39,
BAR5 = 8'h3a,
Card_CIS = 8'h3b,
Sub_ID = 8'h3c,
Expan_ROM = 8'h3d,
Res34h = 8'h3e,
Res38h = 8'h3f,
Max_Min_IR = 8'h40;
// Test_Suit
// This test_suite state type can be configured to suit your own series of tests
// just add and remove these values as necessary.
// Remember to update the change_tests process as well as values assigned in your
// test bench.
// If you're using SILOS to simulate, you also need to update the .ssf symbol file.
parameter no_tests = 8'h50,
initialization = 8'h51,
config = 8'h52,
dma_transfers = 8'h53,
byte_enable_test = 8'h54,
pci_cmd_test = 8'h55,
pci_compliance_test = 5'h56,
customer_specfic_test = 5'h57;
//
reg [7:0] pci_cmd;
reg [7:0] pci_cmd_l;
reg [7:0] config_add;
reg [7:0] test_state;
reg framen_l;
reg [31:0] mem_address;
//assign cmd_mon = cben;
always@(clk)
begin
framen_l <= (!framen);
cmd_mon <= cben;
end
always@(framen_l)
begin
if (! rstn)
begin
pci_cmd <= idle;
pci_cmd_l <= idle;
end
else if (framen_l)
case (cben[3:0])
0 : begin
config_add <= None;
if (pci_cmd_l == IA)
pci_cmd_l <= I_A;
else
begin
pci_cmd <= IA;
pci_cmd_l <= IA;
end
end
1 : begin
config_add = None;
if (pci_cmd_l == SC)
pci_cmd_l <= S_C;
else
begin
pci_cmd <= SC;
pci_cmd_l <= SC;
end
end
2 : begin
config_add <= None;
if (pci_cmd_l == IO_R)
pci_cmd_l <= I_O_R;
else
begin
pci_cmd <= IO_R;
pci_cmd_l <= IO_R;
end
end
3 : begin
config_add <= None;
if (pci_cmd_l == IO_W)
pci_cmd_l <= I_O_W;
else
begin
pci_cmd <= IO_W;
pci_cmd_l <= IO_W;
end
end
4 : begin
config_add <= None;
if (pci_cmd_l == Res4)
pci_cmd_l <= Res_4;
else
begin
pci_cmd <= Res4;
pci_cmd_l <= Res4;
end
end
5 : begin
config_add <= None;
if (pci_cmd_l == Res5)
pci_cmd_l = Res_5;
else
begin
pci_cmd <= Res5;
pci_cmd_l <= Res5;
end
end
6 : begin
mem_address <= ad[31:0];
config_add <= None;
if (pci_cmd_l == MR)
pci_cmd_l <= M_R;
else
begin
pci_cmd <= MR;
pci_cmd_l <= MR;
end
end
7 : begin
mem_address <= ad[31:0];
config_add <= None;
if (pci_cmd_l == MW)
pci_cmd_l <= M_W;
else
begin
pci_cmd <= MW;
pci_cmd_l <= MW;
end
end
8 : begin
config_add = None;
if (pci_cmd_l == Res8)
pci_cmd_l <= Res_8;
else
begin
pci_cmd <= Res8;
pci_cmd_l <= Res8;
end
end
9 : begin
config_add = None;
if (pci_cmd_l == Res9)
pci_cmd_l <= Res_9;
else
begin
pci_cmd <= Res9;
pci_cmd_l <= Res9;
end
end
4'ha : begin
if (pci_cmd_l == CR)
pci_cmd_l <= C_R;
else
begin
pci_cmd <= CR;
pci_cmd_l <= CR;
end
case (ad[7:0])
8'h00 : config_add <= Dev_Vend;
8'h04 : config_add <= Stat_Cmd;
8'h08 : config_add <= Clas_Rev;
8'h0c : config_add <= BHLC;
8'h10 : config_add <= BAR0;
8'h14 : config_add <= BAR1;
8'h18 : config_add <= BAR2;
8'h1c : config_add <= BAR3;
8'h20 : config_add <= BAR4;
8'h24 : config_add <= BAR5;
8'h28 : config_add <= Card_CIS;
8'h2c : config_add <= Sub_ID;
8'h30 : config_add <= Expan_ROM;
8'h34 : config_add <= Res34h;
8'h38 : config_add <= Res38h;
8'h3c : config_add <= Max_Min_IR;
default : config_add <= None;
endcase
end
4'hb : begin
if (pci_cmd_l == CW)
pci_cmd_l <= C_W;
else
begin
pci_cmd <= CW;
pci_cmd_l <= CW;
end
case (ad[7:0])
8'h00 : config_add <= Dev_Vend;
8'h04 : config_add <= Stat_Cmd;
8'h08 : config_add <= Clas_Rev;
8'h0c : config_add <= BHLC;
8'h10 : config_add <= BAR0;
8'h14 : config_add <= BAR1;
8'h18 : config_add <= BAR2;
8'h1c : config_add <= BAR3;
8'h20 : config_add <= BAR4;
8'h24 : config_add <= BAR5;
8'h28 : config_add <= Card_CIS;
8'h2c : config_add <= Sub_ID;
8'h30 : config_add <= Expan_ROM;
8'h34 : config_add <= Res34h;
8'h38 : config_add <= Res38h;
8'h3c : config_add <= Max_Min_IR;
default : config_add <= None;
endcase
end
4'hc : begin
config_add = None;
if (pci_cmd_l == Mem_R_M)
pci_cmd_l <= MRM;
else
begin
pci_cmd <= Mem_R_M;
pci_cmd_l <= Mem_R_M;
end
end
4'hd : begin
config_add = None;
if (pci_cmd_l == D_A_C)
pci_cmd_l <= DAC;
else
begin
pci_cmd <= D_A_C;
pci_cmd_l <= D_A_C;
end
end
4'he : begin
config_add = None;
if (pci_cmd_l == M_R_L)
pci_cmd_l <= MRL;
else
begin
pci_cmd <= M_R_L;
pci_cmd_l <= M_R_L;
end
end
4'hf : begin
config_add = None;
if (pci_cmd_l == M_W_I)
pci_cmd_l <= MWI;
else
begin
pci_cmd <= M_W_I;
pci_cmd_l <= M_W_I;
end
end
default : begin
pci_cmd <= idle;
pci_cmd_l <= idle;
config_add <= None;
end
endcase
end
always@(test_type)
begin
case (test_type)
8'h50 : test_state <= no_tests;
8'h51 : test_state <= initialization;
8'h52 : test_state <= config;
8'h53 : test_state <= dma_transfers;
8'h54 : test_state <= byte_enable_test;
8'h55 : test_state <= pci_cmd_test;
8'h56 : test_state <= customer_specfic_test;
8'h57 : test_state <= pci_compliance_test;
default : test_state <= no_tests;
endcase
end
endmodule
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