dd.vhd

来自「restoring除法器设计 经典算法了」· VHDL 代码 · 共 38 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CHUFA_1 IS
	GENERIC(bit_b:integer:=30;
				bit:integer:=5);
	PORT(CLK:IN STD_LOGIC;
			BEICHUSHU:IN STD_LOGIC_VECTOR(BIT_B-1 DOWNTO 0);--BIT_B-1
			CHUSHU:IN STD_LOGIC_VECTOR(BIT-1 DOWNTO 0);--BIT-1
			SHANG:OUT STD_LOGIC_VECTOR(BIT_B-1 DOWNTO 0) :="000000000000000000000000000000");--BIT_B-1
	END CHUFA_1;
	
ARCHITECTURE LZM OF CHUFA_1 IS
	SIGNAL DIV:STD_LOGIC_VECTOR(BIT DOWNTO 0);--CHUSHU'LENGTH+1==BIT
BEGIN
	
	DIV<='0' & CHUSHU;
	PROCESS(CLK)
		VARIABLE BEI_DIV:STD_LOGIC_VECTOR(BIT_B-1 DOWNTO 0);--BIT_B-1
		VARIABLE BEI_SUB:STD_LOGIC_VECTOR(CHUSHU'LENGTH DOWNTO 0);--4
	BEGIN
		IF CLK='1' AND CLK'EVENT THEN
			BEI_DIV:=BEICHUSHU;
			FOR I IN BIT_B-1 DOWNTO 0 LOOP--7=BEI_DIV'LENGTH=BIT_B-1
				BEI_SUB(CHUSHU'LENGTH DOWNTO 1) :=BEI_SUB(CHUSHU'LENGTH-1 DOWNTO 0);
				BEI_SUB(0):=BEI_DIV(I);
				IF BEI_SUB>=DIV THEN
					SHANG(I)<='1';
					BEI_SUB:=BEI_SUB-DIV;
				ELSE SHANG(I)<='0';
				END IF;
		END LOOP;
		END IF;
	BEI_SUB:=(OTHERS=>'0');
	--YUSHU <= BEI_SUB;
	END PROCESS;
END LZM;