prev_cmp_subcontroller.tan.qmsg

VHDL开发环境

{ "Info" "ITDB_FULL_TCO_RESULT" "clk dr dr_r 7.684 ns register " "Info: tco from clock \"clk\" to destination pin \"dr\" through register \"dr_r\" is 7.684 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.853 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.987 ns) + CELL(0.602 ns) 2.853 ns dr_r 3 REG LCFF_X12_Y21_N29 2 " "Info: 3: + IC(0.987 ns) + CELL(0.602 ns) = 2.853 ns; Loc. = LCFF_X12_Y21_N29; Fanout = 2; REG Node = 'dr_r'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.589 ns" { clk~clkctrl dr_r } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.06 % ) " "Info: Total cell delay = 1.628 ns ( 57.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.225 ns ( 42.94 % ) " "Info: Total interconnect delay = 1.225 ns ( 42.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk clk~clkctrl dr_r } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk {} clk~combout {} clk~clkctrl {} dr_r {} } { 0.000ns 0.000ns 0.238ns 0.987ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.554 ns + Longest register pin " "Info: + Longest register to pin delay is 4.554 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dr_r 1 REG LCFF_X12_Y21_N29 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y21_N29; Fanout = 2; REG Node = 'dr_r'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { dr_r } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.714 ns) + CELL(2.840 ns) 4.554 ns dr 2 PIN PIN_F3 0 " "Info: 2: + IC(1.714 ns) + CELL(2.840 ns) = 4.554 ns; Loc. = PIN_F3; Fanout = 0; PIN Node = 'dr'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "4.554 ns" { dr_r dr } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.840 ns ( 62.36 % ) " "Info: Total cell delay = 2.840 ns ( 62.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.714 ns ( 37.64 % ) " "Info: Total interconnect delay = 1.714 ns ( 37.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "4.554 ns" { dr_r dr } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "4.554 ns" { dr_r {} dr {} } { 0.000ns 1.714ns } { 0.000ns 2.840ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk clk~clkctrl dr_r } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk {} clk~combout {} clk~clkctrl {} dr_r {} } { 0.000ns 0.000ns 0.238ns 0.987ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "4.554 ns" { dr_r dr } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "4.554 ns" { dr_r {} dr {} } { 0.000ns 1.714ns } { 0.000ns 2.840ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "qin\[10\] disp0\[0\] 17.482 ns Longest " "Info: Longest tpd from source pin \"qin\[10\]\" to destination pin \"disp0\[0\]\" is 17.482 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.844 ns) 0.844 ns qin\[10\] 1 PIN PIN_G5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.844 ns) = 0.844 ns; Loc. = PIN_G5; Fanout = 4; PIN Node = 'qin\[10\]'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { qin[10] } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.980 ns) + CELL(0.322 ns) 7.146 ns Equal8~42 2 COMB LCCOMB_X11_Y21_N4 4 " "Info: 2: + IC(5.980 ns) + CELL(0.322 ns) = 7.146 ns; Loc. = LCCOMB_X11_Y21_N4; Fanout = 4; COMB Node = 'Equal8~42'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "6.302 ns" { qin[10] Equal8~42 } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.836 ns) + CELL(0.485 ns) 8.467 ns Equal11~72 3 COMB LCCOMB_X12_Y21_N16 5 " "Info: 3: + IC(0.836 ns) + CELL(0.485 ns) = 8.467 ns; Loc. = LCCOMB_X12_Y21_N16; Fanout = 5; COMB Node = 'Equal11~72'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.321 ns" { Equal8~42 Equal11~72 } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.853 ns) + CELL(0.542 ns) 9.862 ns Equal12~70 4 COMB LCCOMB_X12_Y21_N10 3 " "Info: 4: + IC(0.853 ns) + CELL(0.542 ns) = 9.862 ns; Loc. = LCCOMB_X12_Y21_N10; Fanout = 3; COMB Node = 'Equal12~70'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.395 ns" { Equal11~72 Equal12~70 } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.555 ns) + CELL(0.521 ns) 10.938 ns Equal13~70 5 COMB LCCOMB_X11_Y21_N28 2 " "Info: 5: + IC(0.555 ns) + CELL(0.521 ns) = 10.938 ns; Loc. = LCCOMB_X11_Y21_N28; Fanout = 2; COMB Node = 'Equal13~70'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.076 ns" { Equal12~70 Equal13~70 } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.866 ns) + CELL(0.457 ns) 12.261 ns WideOr3~43 6 COMB LCCOMB_X13_Y21_N26 2 " "Info: 6: + IC(0.866 ns) + CELL(0.457 ns) = 12.261 ns; Loc. = LCCOMB_X13_Y21_N26; Fanout = 2; COMB Node = 'WideOr3~43'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.323 ns" { Equal13~70 WideOr3~43 } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.308 ns) + CELL(0.521 ns) 13.090 ns WideOr3 7 COMB LCCOMB_X13_Y21_N4 1 " "Info: 7: + IC(0.308 ns) + CELL(0.521 ns) = 13.090 ns; Loc. = LCCOMB_X13_Y21_N4; Fanout = 1; COMB Node = 'WideOr3'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "0.829 ns" { WideOr3~43 WideOr3 } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.562 ns) + CELL(2.830 ns) 17.482 ns disp0\[0\] 8 PIN PIN_H4 0 " "Info: 8: + IC(1.562 ns) + CELL(2.830 ns) = 17.482 ns; Loc. = PIN_H4; Fanout = 0; PIN Node = 'disp0\[0\]'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "4.392 ns" { WideOr3 disp0[0] } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.522 ns ( 37.31 % ) " "Info: Total cell delay = 6.522 ns ( 37.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.960 ns ( 62.69 % ) " "Info: Total interconnect delay = 10.960 ns ( 62.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "17.482 ns" { qin[10] Equal8~42 Equal11~72 Equal12~70 Equal13~70 WideOr3~43 WideOr3 disp0[0] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "17.482 ns" { qin[10] {} qin[10]~combout {} Equal8~42 {} Equal11~72 {} Equal12~70 {} Equal13~70 {} WideOr3~43 {} WideOr3 {} disp0[0] {} } { 0.000ns 0.000ns 5.980ns 0.836ns 0.853ns 0.555ns 0.866ns 0.308ns 1.562ns } { 0.000ns 0.844ns 0.322ns 0.485ns 0.542ns 0.521ns 0.457ns 0.521ns 2.830ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "downkey_d downkey clk 0.138 ns register " "Info: th for register \"downkey_d\" (data pin = \"downkey\", clock pin = \"clk\") is 0.138 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.853 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.987 ns) + CELL(0.602 ns) 2.853 ns downkey_d 3 REG LCFF_X12_Y21_N3 1 " "Info: 3: + IC(0.987 ns) + CELL(0.602 ns) = 2.853 ns; Loc. = LCFF_X12_Y21_N3; Fanout = 1; REG Node = 'downkey_d'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.589 ns" { clk~clkctrl downkey_d } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.06 % ) " "Info: Total cell delay = 1.628 ns ( 57.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.225 ns ( 42.94 % ) " "Info: Total interconnect delay = 1.225 ns ( 42.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk clk~clkctrl downkey_d } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk {} clk~combout {} clk~clkctrl {} downkey_d {} } { 0.000ns 0.000ns 0.238ns 0.987ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.001 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.001 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns downkey 1 PIN PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; PIN Node = 'downkey'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { downkey } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.562 ns) + CELL(0.413 ns) 3.001 ns downkey_d 2 REG LCFF_X12_Y21_N3 1 " "Info: 2: + IC(1.562 ns) + CELL(0.413 ns) = 3.001 ns; Loc. = LCFF_X12_Y21_N3; Fanout = 1; REG Node = 'downkey_d'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.975 ns" { downkey downkey_d } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.439 ns ( 47.95 % ) " "Info: Total cell delay = 1.439 ns ( 47.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.562 ns ( 52.05 % ) " "Info: Total interconnect delay = 1.562 ns ( 52.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "3.001 ns" { downkey downkey_d } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "3.001 ns" { downkey {} downkey~combout {} downkey_d {} } { 0.000ns 0.000ns 1.562ns } { 0.000ns 1.026ns 0.413ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk clk~clkctrl downkey_d } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk {} clk~combout {} clk~clkctrl {} downkey_d {} } { 0.000ns 0.000ns 0.238ns 0.987ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "3.001 ns" { downkey downkey_d } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "3.001 ns" { downkey {} downkey~combout {} downkey_d {} } { 0.000ns 0.000ns 1.562ns } { 0.000ns 1.026ns 0.413ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}