prev_cmp_subcontroller.tan.qmsg

VHDL开发环境

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 10 -1 0 } } { "d:/program files/altera/72sp3/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72sp3/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register upkey_d ur_r 380.08 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 380.08 MHz between source register \"upkey_d\" and destination register \"ur_r\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.631 ns " "Info: fmax restricted to clock pin edge rate 2.631 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.542 ns + Longest register register " "Info: + Longest register to register delay is 1.542 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns upkey_d 1 REG LCFF_X12_Y21_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y21_N7; Fanout = 2; REG Node = 'upkey_d'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { upkey_d } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.358 ns) 0.358 ns ur_r~28 2 COMB LCCOMB_X12_Y21_N6 1 " "Info: 2: + IC(0.000 ns) + CELL(0.358 ns) = 0.358 ns; Loc. = LCCOMB_X12_Y21_N6; Fanout = 1; COMB Node = 'ur_r~28'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "0.358 ns" { upkey_d ur_r~28 } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.567 ns) + CELL(0.521 ns) 1.446 ns ur_r~29 3 COMB LCCOMB_X12_Y21_N8 1 " "Info: 3: + IC(0.567 ns) + CELL(0.521 ns) = 1.446 ns; Loc. = LCCOMB_X12_Y21_N8; Fanout = 1; COMB Node = 'ur_r~29'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.088 ns" { ur_r~28 ur_r~29 } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 1.542 ns ur_r 4 REG LCFF_X12_Y21_N9 2 " "Info: 4: + IC(0.000 ns) + CELL(0.096 ns) = 1.542 ns; Loc. = LCFF_X12_Y21_N9; Fanout = 2; REG Node = 'ur_r'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { ur_r~29 ur_r } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.975 ns ( 63.23 % ) " "Info: Total cell delay = 0.975 ns ( 63.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.567 ns ( 36.77 % ) " "Info: Total interconnect delay = 0.567 ns ( 36.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.542 ns" { upkey_d ur_r~28 ur_r~29 ur_r } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "1.542 ns" { upkey_d {} ur_r~28 {} ur_r~29 {} ur_r {} } { 0.000ns 0.000ns 0.567ns 0.000ns } { 0.000ns 0.358ns 0.521ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.853 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.987 ns) + CELL(0.602 ns) 2.853 ns ur_r 3 REG LCFF_X12_Y21_N9 2 " "Info: 3: + IC(0.987 ns) + CELL(0.602 ns) = 2.853 ns; Loc. = LCFF_X12_Y21_N9; Fanout = 2; REG Node = 'ur_r'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.589 ns" { clk~clkctrl ur_r } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.06 % ) " "Info: Total cell delay = 1.628 ns ( 57.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.225 ns ( 42.94 % ) " "Info: Total interconnect delay = 1.225 ns ( 42.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk clk~clkctrl ur_r } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk {} clk~combout {} clk~clkctrl {} ur_r {} } { 0.000ns 0.000ns 0.238ns 0.987ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.853 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.987 ns) + CELL(0.602 ns) 2.853 ns upkey_d 3 REG LCFF_X12_Y21_N7 2 " "Info: 3: + IC(0.987 ns) + CELL(0.602 ns) = 2.853 ns; Loc. = LCFF_X12_Y21_N7; Fanout = 2; REG Node = 'upkey_d'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.589 ns" { clk~clkctrl upkey_d } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.06 % ) " "Info: Total cell delay = 1.628 ns ( 57.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.225 ns ( 42.94 % ) " "Info: Total interconnect delay = 1.225 ns ( 42.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk clk~clkctrl upkey_d } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk {} clk~combout {} clk~clkctrl {} upkey_d {} } { 0.000ns 0.000ns 0.238ns 0.987ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk clk~clkctrl ur_r } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk {} clk~combout {} clk~clkctrl {} ur_r {} } { 0.000ns 0.000ns 0.238ns 0.987ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk clk~clkctrl upkey_d } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk {} clk~combout {} clk~clkctrl {} upkey_d {} } { 0.000ns 0.000ns 0.238ns 0.987ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.542 ns" { upkey_d ur_r~28 ur_r~29 ur_r } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "1.542 ns" { upkey_d {} ur_r~28 {} ur_r~29 {} ur_r {} } { 0.000ns 0.000ns 0.567ns 0.000ns } { 0.000ns 0.358ns 0.521ns 0.096ns } "" } } { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk clk~clkctrl ur_r } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk {} clk~combout {} clk~clkctrl {} ur_r {} } { 0.000ns 0.000ns 0.238ns 0.987ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk clk~clkctrl upkey_d } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk {} clk~combout {} clk~clkctrl {} upkey_d {} } { 0.000ns 0.000ns 0.238ns 0.987ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { ur_r } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { ur_r {} } {  } {  } "" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 48 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "ur_r qin\[10\] clk 7.070 ns register " "Info: tsu for register \"ur_r\" (data pin = \"qin\[10\]\", clock pin = \"clk\") is 7.070 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.961 ns + Longest pin register " "Info: + Longest pin to register delay is 9.961 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.844 ns) 0.844 ns qin\[10\] 1 PIN PIN_G5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.844 ns) = 0.844 ns; Loc. = PIN_G5; Fanout = 4; PIN Node = 'qin\[10\]'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { qin[10] } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.980 ns) + CELL(0.322 ns) 7.146 ns Equal8~42 2 COMB LCCOMB_X11_Y21_N4 4 " "Info: 2: + IC(5.980 ns) + CELL(0.322 ns) = 7.146 ns; Loc. = LCCOMB_X11_Y21_N4; Fanout = 4; COMB Node = 'Equal8~42'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "6.302 ns" { qin[10] Equal8~42 } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.836 ns) + CELL(0.485 ns) 8.467 ns Equal11~72 3 COMB LCCOMB_X12_Y21_N16 5 " "Info: 3: + IC(0.836 ns) + CELL(0.485 ns) = 8.467 ns; Loc. = LCCOMB_X12_Y21_N16; Fanout = 5; COMB Node = 'Equal11~72'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.321 ns" { Equal8~42 Equal11~72 } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.853 ns) + CELL(0.545 ns) 9.865 ns ur_r~29 4 COMB LCCOMB_X12_Y21_N8 1 " "Info: 4: + IC(0.853 ns) + CELL(0.545 ns) = 9.865 ns; Loc. = LCCOMB_X12_Y21_N8; Fanout = 1; COMB Node = 'ur_r~29'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.398 ns" { Equal11~72 ur_r~29 } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 9.961 ns ur_r 5 REG LCFF_X12_Y21_N9 2 " "Info: 5: + IC(0.000 ns) + CELL(0.096 ns) = 9.961 ns; Loc. = LCFF_X12_Y21_N9; Fanout = 2; REG Node = 'ur_r'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { ur_r~29 ur_r } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.292 ns ( 23.01 % ) " "Info: Total cell delay = 2.292 ns ( 23.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.669 ns ( 76.99 % ) " "Info: Total interconnect delay = 7.669 ns ( 76.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "9.961 ns" { qin[10] Equal8~42 Equal11~72 ur_r~29 ur_r } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "9.961 ns" { qin[10] {} qin[10]~combout {} Equal8~42 {} Equal11~72 {} ur_r~29 {} ur_r {} } { 0.000ns 0.000ns 5.980ns 0.836ns 0.853ns 0.000ns } { 0.000ns 0.844ns 0.322ns 0.485ns 0.545ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.853 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.987 ns) + CELL(0.602 ns) 2.853 ns ur_r 3 REG LCFF_X12_Y21_N9 2 " "Info: 3: + IC(0.987 ns) + CELL(0.602 ns) = 2.853 ns; Loc. = LCFF_X12_Y21_N9; Fanout = 2; REG Node = 'ur_r'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.589 ns" { clk~clkctrl ur_r } "NODE_NAME" } } { "subcontroller.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/subcontroller/subcontroller.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.06 % ) " "Info: Total cell delay = 1.628 ns ( 57.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.225 ns ( 42.94 % ) " "Info: Total interconnect delay = 1.225 ns ( 42.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk clk~clkctrl ur_r } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk {} clk~combout {} clk~clkctrl {} ur_r {} } { 0.000ns 0.000ns 0.238ns 0.987ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "9.961 ns" { qin[10] Equal8~42 Equal11~72 ur_r~29 ur_r } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "9.961 ns" { qin[10] {} qin[10]~combout {} Equal8~42 {} Equal11~72 {} ur_r~29 {} ur_r {} } { 0.000ns 0.000ns 5.980ns 0.836ns 0.853ns 0.000ns } { 0.000ns 0.844ns 0.322ns 0.485ns 0.545ns 0.096ns } "" } } { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk clk~clkctrl ur_r } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk {} clk~combout {} clk~clkctrl {} ur_r {} } { 0.000ns 0.000ns 0.238ns 0.987ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}