prev_cmp_counter.tan.qmsg

VHDL开发环境

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register temp\[0\] temp\[2\] 380.08 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 380.08 MHz between source register \"temp\[0\]\" and destination register \"temp\[2\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.631 ns " "Info: fmax restricted to clock pin edge rate 2.631 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.985 ns + Longest register register " "Info: + Longest register to register delay is 0.985 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp\[0\] 1 REG LCFF_X1_Y25_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y25_N1; Fanout = 4; REG Node = 'temp\[0\]'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { temp[0] } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.368 ns) + CELL(0.521 ns) 0.889 ns temp~152 2 COMB LCCOMB_X1_Y25_N6 1 " "Info: 2: + IC(0.368 ns) + CELL(0.521 ns) = 0.889 ns; Loc. = LCCOMB_X1_Y25_N6; Fanout = 1; COMB Node = 'temp~152'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "0.889 ns" { temp[0] temp~152 } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 0.985 ns temp\[2\] 3 REG LCFF_X1_Y25_N7 4 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 0.985 ns; Loc. = LCFF_X1_Y25_N7; Fanout = 4; REG Node = 'temp\[2\]'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { temp~152 temp[2] } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.617 ns ( 62.64 % ) " "Info: Total cell delay = 0.617 ns ( 62.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.368 ns ( 37.36 % ) " "Info: Total interconnect delay = 0.368 ns ( 37.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "0.985 ns" { temp[0] temp~152 temp[2] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "0.985 ns" { temp[0] {} temp~152 {} temp[2] {} } { 0.000ns 0.368ns 0.000ns } { 0.000ns 0.521ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.860 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.860 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.994 ns) + CELL(0.602 ns) 2.860 ns temp\[2\] 3 REG LCFF_X1_Y25_N7 4 " "Info: 3: + IC(0.994 ns) + CELL(0.602 ns) = 2.860 ns; Loc. = LCFF_X1_Y25_N7; Fanout = 4; REG Node = 'temp\[2\]'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.596 ns" { clk~clkctrl temp[2] } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.92 % ) " "Info: Total cell delay = 1.628 ns ( 56.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.232 ns ( 43.08 % ) " "Info: Total interconnect delay = 1.232 ns ( 43.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { clk clk~clkctrl temp[2] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { clk {} clk~combout {} clk~clkctrl {} temp[2] {} } { 0.000ns 0.000ns 0.238ns 0.994ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.860 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.860 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.994 ns) + CELL(0.602 ns) 2.860 ns temp\[0\] 3 REG LCFF_X1_Y25_N1 4 " "Info: 3: + IC(0.994 ns) + CELL(0.602 ns) = 2.860 ns; Loc. = LCFF_X1_Y25_N1; Fanout = 4; REG Node = 'temp\[0\]'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.596 ns" { clk~clkctrl temp[0] } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.92 % ) " "Info: Total cell delay = 1.628 ns ( 56.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.232 ns ( 43.08 % ) " "Info: Total interconnect delay = 1.232 ns ( 43.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { clk clk~clkctrl temp[0] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { clk {} clk~combout {} clk~clkctrl {} temp[0] {} } { 0.000ns 0.000ns 0.238ns 0.994ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { clk clk~clkctrl temp[2] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { clk {} clk~combout {} clk~clkctrl {} temp[2] {} } { 0.000ns 0.000ns 0.238ns 0.994ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { clk clk~clkctrl temp[0] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { clk {} clk~combout {} clk~clkctrl {} temp[0] {} } { 0.000ns 0.000ns 0.238ns 0.994ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "0.985 ns" { temp[0] temp~152 temp[2] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "0.985 ns" { temp[0] {} temp~152 {} temp[2] {} } { 0.000ns 0.368ns 0.000ns } { 0.000ns 0.521ns 0.096ns } "" } } { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { clk clk~clkctrl temp[2] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { clk {} clk~combout {} clk~clkctrl {} temp[2] {} } { 0.000ns 0.000ns 0.238ns 0.994ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { clk clk~clkctrl temp[0] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { clk {} clk~combout {} clk~clkctrl {} temp[0] {} } { 0.000ns 0.000ns 0.238ns 0.994ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { temp[2] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { temp[2] {} } {  } {  } "" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 23 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "temp\[0\] en clk 4.518 ns register " "Info: tsu for register \"temp\[0\]\" (data pin = \"en\", clock pin = \"clk\") is 4.518 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.416 ns + Longest pin register " "Info: + Longest pin to register delay is 7.416 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.883 ns) 0.883 ns en 1 PIN PIN_B3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.883 ns) = 0.883 ns; Loc. = PIN_B3; Fanout = 1; PIN Node = 'en'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.237 ns) + CELL(0.278 ns) 6.398 ns temp\[0\]~150 2 COMB LCCOMB_X1_Y25_N4 3 " "Info: 2: + IC(5.237 ns) + CELL(0.278 ns) = 6.398 ns; Loc. = LCCOMB_X1_Y25_N4; Fanout = 3; COMB Node = 'temp\[0\]~150'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "5.515 ns" { en temp[0]~150 } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.260 ns) + CELL(0.758 ns) 7.416 ns temp\[0\] 3 REG LCFF_X1_Y25_N1 4 " "Info: 3: + IC(0.260 ns) + CELL(0.758 ns) = 7.416 ns; Loc. = LCFF_X1_Y25_N1; Fanout = 4; REG Node = 'temp\[0\]'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.018 ns" { temp[0]~150 temp[0] } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.919 ns ( 25.88 % ) " "Info: Total cell delay = 1.919 ns ( 25.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.497 ns ( 74.12 % ) " "Info: Total interconnect delay = 5.497 ns ( 74.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "7.416 ns" { en temp[0]~150 temp[0] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "7.416 ns" { en {} en~combout {} temp[0]~150 {} temp[0] {} } { 0.000ns 0.000ns 5.237ns 0.260ns } { 0.000ns 0.883ns 0.278ns 0.758ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.860 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.860 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.994 ns) + CELL(0.602 ns) 2.860 ns temp\[0\] 3 REG LCFF_X1_Y25_N1 4 " "Info: 3: + IC(0.994 ns) + CELL(0.602 ns) = 2.860 ns; Loc. = LCFF_X1_Y25_N1; Fanout = 4; REG Node = 'temp\[0\]'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.596 ns" { clk~clkctrl temp[0] } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.92 % ) " "Info: Total cell delay = 1.628 ns ( 56.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.232 ns ( 43.08 % ) " "Info: Total interconnect delay = 1.232 ns ( 43.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { clk clk~clkctrl temp[0] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { clk {} clk~combout {} clk~clkctrl {} temp[0] {} } { 0.000ns 0.000ns 0.238ns 0.994ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "7.416 ns" { en temp[0]~150 temp[0] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "7.416 ns" { en {} en~combout {} temp[0]~150 {} temp[0] {} } { 0.000ns 0.000ns 5.237ns 0.260ns } { 0.000ns 0.883ns 0.278ns 0.758ns } "" } } { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { clk clk~clkctrl temp[0] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { clk {} clk~combout {} clk~clkctrl {} temp[0] {} } { 0.000ns 0.000ns 0.238ns 0.994ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[2\] temp\[2\] 6.913 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[2\]\" through register \"temp\[2\]\" is 6.913 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.860 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.860 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.994 ns) + CELL(0.602 ns) 2.860 ns temp\[2\] 3 REG LCFF_X1_Y25_N7 4 " "Info: 3: + IC(0.994 ns) + CELL(0.602 ns) = 2.860 ns; Loc. = LCFF_X1_Y25_N7; Fanout = 4; REG Node = 'temp\[2\]'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.596 ns" { clk~clkctrl temp[2] } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.92 % ) " "Info: Total cell delay = 1.628 ns ( 56.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.232 ns ( 43.08 % ) " "Info: Total interconnect delay = 1.232 ns ( 43.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { clk clk~clkctrl temp[2] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { clk {} clk~combout {} clk~clkctrl {} temp[2] {} } { 0.000ns 0.000ns 0.238ns 0.994ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.776 ns + Longest register pin " "Info: + Longest register to pin delay is 3.776 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp\[2\] 1 REG LCFF_X1_Y25_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y25_N7; Fanout = 4; REG Node = 'temp\[2\]'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { temp[2] } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.936 ns) + CELL(2.840 ns) 3.776 ns q\[2\] 2 PIN PIN_E3 0 " "Info: 2: + IC(0.936 ns) + CELL(2.840 ns) = 3.776 ns; Loc. = PIN_E3; Fanout = 0; PIN Node = 'q\[2\]'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "3.776 ns" { temp[2] q[2] } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.840 ns ( 75.21 % ) " "Info: Total cell delay = 2.840 ns ( 75.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.936 ns ( 24.79 % ) " "Info: Total interconnect delay = 0.936 ns ( 24.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "3.776 ns" { temp[2] q[2] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "3.776 ns" { temp[2] {} q[2] {} } { 0.000ns 0.936ns } { 0.000ns 2.840ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { clk clk~clkctrl temp[2] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { clk {} clk~combout {} clk~clkctrl {} temp[2] {} } { 0.000ns 0.000ns 0.238ns 0.994ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "3.776 ns" { temp[2] q[2] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "3.776 ns" { temp[2] {} q[2] {} } { 0.000ns 0.936ns } { 0.000ns 2.840ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "temp\[1\] preset clk -3.557 ns register " "Info: th for register \"temp\[1\]\" (data pin = \"preset\", clock pin = \"clk\") is -3.557 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.860 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.860 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.994 ns) + CELL(0.602 ns) 2.860 ns temp\[1\] 3 REG LCFF_X1_Y25_N3 4 " "Info: 3: + IC(0.994 ns) + CELL(0.602 ns) = 2.860 ns; Loc. = LCFF_X1_Y25_N3; Fanout = 4; REG Node = 'temp\[1\]'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "1.596 ns" { clk~clkctrl temp[1] } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.92 % ) " "Info: Total cell delay = 1.628 ns ( 56.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.232 ns ( 43.08 % ) " "Info: Total interconnect delay = 1.232 ns ( 43.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { clk clk~clkctrl temp[1] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { clk {} clk~combout {} clk~clkctrl {} temp[1] {} } { 0.000ns 0.000ns 0.238ns 0.994ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.703 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.703 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.873 ns) 0.873 ns preset 1 PIN PIN_B4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.873 ns) = 0.873 ns; Loc. = PIN_B4; Fanout = 4; PIN Node = 'preset'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "" { preset } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.279 ns) + CELL(0.455 ns) 6.607 ns temp~151 2 COMB LCCOMB_X1_Y25_N2 1 " "Info: 2: + IC(5.279 ns) + CELL(0.455 ns) = 6.607 ns; Loc. = LCCOMB_X1_Y25_N2; Fanout = 1; COMB Node = 'temp~151'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "5.734 ns" { preset temp~151 } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 6.703 ns temp\[1\] 3 REG LCFF_X1_Y25_N3 4 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 6.703 ns; Loc. = LCFF_X1_Y25_N3; Fanout = 4; REG Node = 'temp\[1\]'" {  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { temp~151 temp[1] } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/program files/altera/Program/LOB/maincontroller/counter/counter.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.424 ns ( 21.24 % ) " "Info: Total cell delay = 1.424 ns ( 21.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.279 ns ( 78.76 % ) " "Info: Total interconnect delay = 5.279 ns ( 78.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "6.703 ns" { preset temp~151 temp[1] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "6.703 ns" { preset {} preset~combout {} temp~151 {} temp[1] {} } { 0.000ns 0.000ns 5.279ns 0.000ns } { 0.000ns 0.873ns 0.455ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { clk clk~clkctrl temp[1] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { clk {} clk~combout {} clk~clkctrl {} temp[1] {} } { 0.000ns 0.000ns 0.238ns 0.994ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72sp3/quartus/bin/TimingClosureFloorplan.fld" "" "6.703 ns" { preset temp~151 temp[1] } "NODE_NAME" } } { "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72sp3/quartus/bin/Technology_Viewer.qrui" "6.703 ns" { preset {} preset~combout {} temp~151 {} temp[1] {} } { 0.000ns 0.000ns 5.279ns 0.000ns } { 0.000ns 0.873ns 0.455ns 0.096ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}