counter.hier_info

VHDL开发环境

|counter
clk => temp[2].CLK
clk => temp[1].CLK
clk => temp[0].CLK
preset => temp~8.OUTPUTSELECT
preset => temp~7.OUTPUTSELECT
preset => temp~6.OUTPUTSELECT
clr => temp[2].ACLR
clr => temp[1].ACLR
clr => temp[0].ACLR
en => temp~5.OUTPUTSELECT
en => temp~4.OUTPUTSELECT
en => temp~3.OUTPUTSELECT
q[0] <= temp[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= temp[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= temp[2].DB_MAX_OUTPUT_PORT_TYPE