memctrl.v

8051的Verilog实现

      begin
      addrbuff <= 16'b0000000000000000 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Address buffer register write
      //--------------------------------
      begin
      if (intcall)      // Interrupt call
         begin
         addrbuff[7:0] <= {intvect, 3'b011} ; 
         end
      else if (membufflwe)
         begin
         addrbuff[7:0] <= memdatai ; 
         end
      else if (rambufflwe)
         begin
         addrbuff[7:0] <= ramdatai ; 
         end 
      if (intcall)      // Interrupt call
         begin
         addrbuff[15:8] <= 8'b00000000 ; 
         end
      else if (membuffhwe)
         begin
         addrbuff[15:8] <= memdatai ; 
         end
      else if (rambuffhwe)
         begin
         addrbuff[15:8] <= ramdatai ; 
         end
      else if (instrbuffwe)
         begin
         addrbuff[10:8] <= instr[7:5] ; 
         addrbuff[15:11] <= pc_inc[15:11] ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   // Memory to ACC write enable
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : mem2acc_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      mem2acc <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
      if (
            (
               (instr == MOVX_A_IR0 |
               instr == MOVX_A_IR1 |
               instr == MOVX_A_IDPTR)
               &
               (
                  (stretch      == 3'b000  & cycle == 1 & !pmw) |
                  (psstretch    == 3'b000  & cycle == 1 &  pmw) |
                  (stretchcount == 4'b0010 & cycle == 2) |
                  (stretchcount == 4'b0001 & !mem_ack_psack_in) 
               )
            
            )
            |
            (
               (instr == MOVC_A_PC |
               instr == MOVC_A_DPTR)
               &
               (
                  (cycle == 1) |
                  (cycle == 2 & !mempsackint)
               )
            )
         )
         begin
         mem2acc <= 1'b1 ; 
         end
      else
         begin
         if ((instr == MOVX_A_IR0 |
              instr == MOVX_A_IR1 |
              instr == MOVX_A_IDPTR) &
             ((stretch   == 3'b000 & !pmw) |
              (psstretch == 3'b000 &  pmw)
             )
            )
            begin
            if (mem_ack_psack_in)
               begin
               mem2acc <= 1'b0 ; 
               end
            end
            else
            begin    
            mem2acc <= 1'b0 ;
            end
         end 
      end  
   end 

   //------------------------------------------------------------------
   // RAM to MemAddr write enable
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : ram2memaddr_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      ram2memaddr <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
      if (
            (
               (instr == MOVX_A_IR0) |
               (instr == MOVX_A_IR1)
            )
            &
            (((stretch   != 3'b000 & !pmw) |
              (psstretch != 3'b000 &  pmw)
             )
             &
             ((stretch   != 3'b001 & !pmw) | 
              (psstretch != 3'b001 &  pmw)
             )
             &
             (cycle == 1 |
              (cycle == 2 & 
               (stretchcount == 4'b0011 |
                stretchcount == 4'b0100 |
                stretchcount == 4'b0101 |
                stretchcount == 4'b0110 |
                stretchcount == 4'b0111 |
                stretchcount == 4'b1000
               )
              )
             )
            )  
         )
         begin
         ram2memaddr <= 1'b1 ; 
         end
      else if
         (
            (
               (instr == MOVX_IR0_A) |
               (instr == MOVX_IR1_A)
            )
            &
            (
               ((stretch   != 3'b000 & !pmw) |
                (psstretch != 3'b000 &  pmw)
               ) 
               &
               (cycle == 1 | 
                (((stretch   != 3'b001 & !pmw) |
                  (psstretch != 3'b001 &  pmw)
                 ) & 
                 cycle == 2
                )
                |
                (cycle == 3 & 
                 (stretchcount == 4'b0011 |
                  stretchcount == 4'b0100 |
                  stretchcount == 4'b0101 |
                  stretchcount == 4'b0110 | 
                  stretchcount == 4'b0111
                 )
                )
               )
            )  
         )
         begin
         ram2memaddr <= 1'b1 ; 
         end
      else
         begin
         ram2memaddr <= 1'b0 ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   // Program store write enable
   //  still inactive (optional feature)
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : mempswr_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      mempswr <= 1'b0 ; 
      end
   else
      begin
      //-----------------------------------
      // Synchronous write
      //-----------------------------------  
      if ((
             (instr == MOVX_IR0_A) |
             (instr == MOVX_IR1_A) |
             (instr == MOVX_IDPTR_A)
          ) & pmw &
          (cycle == 2 |
             (cycle == 3 & 
                (stretchcount == 4'b0010 | 
                 stretchcount == 4'b0011 | 
                 stretchcount == 4'b0100 | 
                 stretchcount == 4'b0101 | 
                 stretchcount == 4'b0110 | 
                 stretchcount == 4'b0111
                )
             )        
          )
         )
         begin
         mempswr <= 1'b1;
         end
      else
         begin
         if (movxend)
            begin
            mempswr <= 1'b0;     
            end
         end
      end
   end 

   //------------------------------------------------------------------
   // Program store read enable for MOVC instructions only
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : storefetche_hand_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      storefetche <= 1'b0 ; 
      end
   else
      begin
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      if (
            (
               (cycle == 1) |
               (cycle == 2 & !mempsackint)
            ) &
            (
               instr == MOVC_A_PC |
               instr == MOVC_A_DPTR
            )
         )
         begin
         storefetche <= 1'b1 ; 
         end
      else
         begin
         storefetche <= 1'b0 ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   // Program store read enable
   //  combinational output
   //  high active
   //------------------------------------------------------------------
   always @(mempsrdrst or 
            codefetche or
            debugfetche or
            datafetche or 
            storefetche)
   begin : mempsrd_proc
   //------------------------------------------------------------------
   if (mempsrdrst)
      //-----------------------------------
      // Combinational reset
      //-----------------------------------
      begin
      mempsrd_int = 1'b0 ; 
      end
   else
      begin
      //-----------------------------------
      // Combinational write
      //-----------------------------------
      if (codefetche | debugfetche | datafetche | storefetche)
         begin
         mempsrd_int = 1'b1 ; 
         end
      else
         begin
         mempsrd_int = 1'b0 ; 
         end 
      end 
   end 

   assign mempsrd = mempsrd_int | (memrd_int & pmw) ;

   //------------------------------------------------------------------
   // Memory write enable
   //  registered output
   //  high active
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : memwr_drv
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      memwr <= 1'b0 ; 
      end
      else
      begin
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      if (
            (
               (instr == MOVX_IR0_A) |
               (instr == MOVX_IR1_A) |
               (instr == MOVX_IDPTR_A)
            )
            & !pmw &
            (cycle == 2 |
             (cycle == 3 & 
              (stretchcount == 4'b0010 |
               stretchcount == 4'b0011 | 
               stretchcount == 4'b0100 | 
               stretchcount == 4'b0101 | 
               stretchcount == 4'b0110 | 
               stretchcount == 4'b0111
              )
             )        
            )
         )
         begin
         memwr <= 1'b1 ; 
         end
      else
         begin
         if (movxend)
            begin
            memwr <= 1'b0 ;     
            end
         end 
      end  
   end 

   //------------------------------------------------------------------
   // Memory read enable
   //  registered output
   //  high active
   //