serial0.v

8051的Verilog实现

               begin
               rxd0_val <= rxd0_inff ; 
               end 
            end
         else
            begin
            if (clk_count[2])
               begin
               rxd0_val <= rxd0_inff ; 
               end 
            end 
         end
      
      default :  // mode 1,2,3
         begin
         if (rxd0_vec == 3'b001 |
             rxd0_vec == 3'b010 |
             rxd0_vec == 3'b100 |
             rxd0_vec == 3'b000)
            begin
            rxd0_val <= 1'b0 ; 
            end
         else
            begin
            rxd0_val <= 1'b1 ; 
            end 
         end
      
      endcase 
      end  
   end 

   //------------------------------------------------------------------
   // Rising edge detection on the r_start 
   // r_start_rise is high active during single clk period
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : r_start_rise_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      r_start_rise <= 1'b0 ; 
      r_start_ff <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Falling edge detection
      //--------------------------------
      begin
      if (r_start & !r_start_ff)
         begin
         r_start_rise <= 1'b1 ; 
         end
      else
         begin
         r_start_rise <= 1'b0 ; 
         end 
      
      //--------------------------------
      // r_start flip-flop
      //--------------------------------
      r_start_ff <= r_start ; 
      
      end  
   end 

   //------------------------------------------------------------------
   // Falling edge detection on the r_start 
   // r_start_fall is high active during single clk period
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : r_start_fall_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      r_start_fall <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Falling edge detection
      //--------------------------------
      begin
      if (!r_start & r_start_ff)
         begin
         r_start_fall <= 1'b1 ; 
         end
      else
         begin
         r_start_fall <= 1'b0 ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   // Falling edge detection on the ri0
   // ri0_fall is high active during single clk period
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : ri0_fall_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      ri0_fall <= 1'b0 ; 
      ri0_ff <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Falling edge detection
      //--------------------------------
      begin
      if (!(s0con[0]) & ri0_ff)
         begin
         ri0_fall <= 1'b1 ; 
         end
      else
         begin
         ri0_fall <= 1'b0 ; 
         end 
      
      //--------------------------------
      // t0 input flip-flop
      //--------------------------------
      ri0_ff <= s0con[0] ; 
      
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : receive_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      s0buf_r <= S0BUF_RV ; 
      r_baud_count <= 4'b0000 ; 
      receive <= 1'b0 ; 
      r_shift_reg <= 11'b11111111111 ; 
      r_shift_count <= 4'b0000 ; 
      r_start <= 1'b0 ; 
      r_start_ok <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // receive clk divide by 16
      //--------------------------------
      begin
      if (rxd0_fall & !r_start)
         begin
         r_baud_count <= 4'b0000 ; 
         end
      else if (b_clk)
         begin
         r_baud_count <= r_baud_count + 1'b1 ; 
         end 
      //--------------------------------
      // Receive register shift
      //--------------------------------
      case (s0con[7:6])
      //-----------------------------
      // Mode 0
      //-----------------------------
      2'b00 :
         begin
         if (receive & clk_count == 4'b1011)
            begin
            r_shift_reg[9:0] <= r_shift_reg[10:1] ; 
            r_shift_reg[10] <= r_shift_temp ; 
            r_shift_count <= r_shift_count - 1'b1 ; 
            if (r_shift_count == 4'b0001)
               begin
               r_start <= 1'b0 ; 
               receive <= 1'b0 ; 
               end 
            end
         else if (receive & clk_count == 4'b1001)
            begin
            r_shift_temp <= rxd0_inff ; 
            end 
         end
      
      //-----------------------------
      // Mode 1
      //-----------------------------
      2'b01 :
         begin
         if (r_baud_count == 4'b1001 &
             b_clk &
             r_start &
             ~(r_shift_count == 4'b0000)
             )
            begin
            r_shift_reg[9:0] <= r_shift_reg[10:1] ; 
            r_shift_reg[10] <= rxd0_val ; 
            r_shift_count <= r_shift_count - 1'b1 ; 
            if (r_shift_count == 4'b0001)
               begin
               r_start <= 1'b0 ; 
               receive <= 1'b0 ; 
               end 
            
            if (r_shift_count == 4'b1010)
               begin
               if (!rxd0_val)
                  begin
                  r_start_ok <= 1'b1 ; 
                  end
               else
                  begin
                  r_start <= 1'b0 ; 
                  receive <= 1'b0 ; 
                  r_shift_count <= 4'b0000 ; 
                  end 
               end 
            end 
            
         if (r_start_fall & r_start_ok)
            begin
            r_start_ok <= 1'b0 ; 
            end 
         
         end
      
      //-----------------------------
      // Mode 2, 3
      //-----------------------------
      default :
         begin
         if (r_baud_count == 4'b1001 &
             b_clk &
             receive &
             ~(r_shift_count == 4'b0000)
             )
            begin
            r_shift_reg[9:0] <= r_shift_reg[10:1] ; 
            r_shift_reg[10] <= rxd0_val ; 
            r_shift_count <= r_shift_count - 1'b1 ; 
            if (r_shift_count == 4'b0010)
               begin
               r_start <= 1'b0 ; 
               end 
            
            if (r_shift_count == 4'b0001)
               begin
               receive <= 1'b0 ; 
               end 
            
            if (r_shift_count == 4'b1011)
               begin
               if (!rxd0_val)
                  begin
                  r_start_ok <= 1'b1 ; 
                  end
               else
                  begin
                  r_start <= 1'b0 ; 
                  receive <= 1'b0 ; 
                  r_shift_count <= 4'b0000 ; 
                  end 
               end 
            end 
            
         if (r_start_fall & r_start_ok)
            begin
            r_start_ok <= 1'b0 ; 
            end 
         
         end
      endcase 
      
      if (clk_count == 4'b1011 & r_start)
         begin
         if (!receive)
            begin
            receive <= 1'b1 ; 
            end 
         end 
         
      //--------------------------------
      // Receive shift enable
      //--------------------------------
      if (
            (
               rxd0_fall &
               (~(s0con[7:6] == 2'b00) &
               (s0con[4]) &
               r_shift_count == 4'b0000)
            )
            |
            (
               ri0_fall &
               s0con[7:6] == 2'b00 &
               (s0con[4])
            )
         )
         begin
         r_start <= 1'b1 ; 
         end 
      
      //--------------------------------
      // Receive count load
      //--------------------------------
      // Mode 0
      //--------------------------------
      if (s0con[7:6] == 2'b00)
         begin
         if (ri0_fall & (s0con[4]))
            begin
            r_shift_count <= 4'b1000 ; 
            end 
         end
         
      //--------------------------------
      // Mode 1, 2, 3
      //--------------------------------
      else if (r_start_rise & r_shift_count == 4'b0000)
         begin
         if (s0con[7:6] == 2'b01)
            begin
            r_shift_count <= 4'b1010 ; 
            end
         else
            begin
            r_shift_count <= 4'b1011 ; 
            end 
         end 
      
      if (r_start_fall)
         begin
         if (s0con[7:6] == 2'b00)
            begin
            s0buf_r <= r_shift_reg[10:3] ; 
            end
         else
            begin
            if (r_start_ok & !(s0con[0]))
               begin
               if (s0con[5])
                  begin
                  if (r_shift_reg[10])
                     begin
                     s0buf_r <= r_shift_reg[9:2] ; 
                     end 
                  end
               else
                  begin
                  s0buf_r <= r_shift_reg[9:2] ; 
                  end 
               end 
            end 
         end 
      end  
   end 
   
   //------------------------------------------------------------------
   // Special Function registers read
   //------------------------------------------------------------------
   assign sfrdataser0 =
      (sfraddr == S0CON_ID) ? s0con :
      (sfraddr == S0BUF_ID) ? s0buf_r :
      (sfraddr == S0RELL_ID) ? s0rell :
      (sfraddr == S0RELH_ID) ? s0relh :
      adcon ;


endmodule  //  module SERIAL_0

//*******************************************************************--